Advertisement

Power-Performance Trade-Offs in Second Level Memory Used by an ARM-Like RISC Architecture

  • Kiran Puttaswamy
  • Lakshmi Narasimhan Chakrapani
  • Kyu-Won Choi
  • Yuvraj Singh Dhillon
  • Utku Diril
  • Pinar Korkmaz
  • Kyoung-Keun Lee
  • Jun Cheol Park
  • Abhijit Chatterjee
  • Peeter Ellervee
  • Vincent John MooneyIII
  • Krishna V. Palem
  • Weng-Fai Wong
Part of the Series in Computer Science book series (SCS)

Abstract

Power consumption is an important dimension in microprocessor and digital system design. This is especially true in the embedded setting where microprocessors have to operate without the luxury of a large power supply or cooling structures. In this paper, we describe an infrastructure setup for the study of power-performance tradeoffs in microprocessor architecture and compiler optimizations. This infrastructure distinguishes itself from those already proposed in the literature in its use of power estimations based on synthesis of the architecture and the full integration of a well-established optimizing compiler framework. We present some preliminary results where we show how the circuit level and architectural techniques can be combined to save overall system power. In particular we reduce the clock frequency and supply voltage of level two memory accesses (circuit level technique) and compensate for the resulting increase in the completion time by implementing a non-blocking store buffer (architectural technique) resulting in up to 39% less power and up to 28% less energy on a set of candidate benchmarks.

Keywords

Supply Voltage Print Circuit Board Power Dissipation Switching Activity Compiler Optimization 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    J. Montanaro, R.T. Witek, K. Anne,, A. J. Black, E. M. Cooper, D. W. Dobberpuhl, P. M. Donahue et. al., “A 160 Mhz 32 B 0.5 W CMOS RISC Microprocessor, ” IEEE journal of Solid-State Circuits, Vol. 31, No. 11, pp. 1703–1714, November 1996.CrossRefGoogle Scholar
  2. [2]
    D. Seal, ARM Architecture Reference Manual, Second Edition, Addison Wesley Publications, England, 2001.D. Seal et. al., ARM Architecture Reference Manual, Addison Wesley Publications, 2001.Google Scholar
  3. [3]
    S. Furber, ARM System Architecture, First Edition, Addison Wesley Publications, England, 1996.Google Scholar
  4. [4]
    K. Ghose et. al., “Exploiting Bit-Slice Inactivities for Reducing Energy Requirements of Superscalar Processors,” Kool Chips workshop in association with MICRO33, Monterey, California, December 2000.Google Scholar
  5. [5]
    V. Tiwari and M. Tien-Chien Lee, “Power Analysis of a 32-bit Embedded Microcontroller,” Proceedings of the Asia and South Pacific Design Automation Conference, pp. 141–148, August 1995.Google Scholar
  6. [6]
    G. C. Cardarilli, M. Salmeri, A. Salsano and O.Simonelli, “Bus Architecture for Low Power VLSI Digital Circuits,” IEEE International Symposium on Circuit and Systems, pp. 21–24, May 1996.Google Scholar
  7. [7]
    B. Prince, Semiconductor Memories, Second Edition, John Wiley and Sons, England, 1996.Google Scholar
  8. [8]
    R. J. Evans and P. D. Franzion, “Energy Consumption Modeling and Optimization for SRAMs,” IEEE Journal of Solid State Circuits, Vol. 30, No. 5, pp. 571–579, May 1995.CrossRefGoogle Scholar
  9. [9]
    Trimaran Consortium, http://www.trimaran.org
  10. [10]
    Synopsys, Inc., http://www.synopsys.com
  11. [11]
    LEDA Systems, Inc., http://www.ledasys.com
  12. [12]
    D. M. Pozar, Microwave Engineering, Second Edition, John Wiley & Sons Inc., USA, 1997.Google Scholar
  13. [13]
    http://www.eecs.umich.edu/;jringenb/power/
  14. [14]
    http://www.eecs.umich.edu/taustin/simplescalar
  15. [15]
    A. Chandrakasan and R. Brodersen, Low Power CMOS Design, John Wiley & Sons Inc., USA, 1998.Google Scholar
  16. [16]
    P. R. Panda and N. Dutt, “Low Power Memory Mapping through Reducing Address Bus Activity,” IEEE Transactions on VLSI Systems, Vol. 7, No. 3, pp. 309–320, September 1999.CrossRefGoogle Scholar
  17. [17]
    N. Chang, K. Kim and H. G. Lee, “Cycle Accurate Energy Consumption Measurement and Analysis: Case Study of ARM7TDMI,” Proceedings of the International Symposium on Low Power Electronics and Design, pp. 185–190, July 2000.Google Scholar
  18. [18]
    A. Sinha, A. Wang and A. P. Chandrakasan, “Algorithmic Transforms for Efficient Energy Scalable Computation,” Proceedings of the International Symposium on Low Power Electronics and Design, pp. 31–36, July 2000.Google Scholar
  19. [19]
    M. Powell, S. Yang, B. Falsafi, K. Roy and T. N. Vijaykumar, “Gated Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories,” Proceedings of the International Symposium on Low Power Electronics and Design, pp. 90–95, July 2000.Google Scholar
  20. [20]
    Denalisoft, Inc., http://www.denalisoft.com
  21. [21]
    Compaq, Inc., http://www.compaq.com
  22. [22]
  23. [23]
    D. Liu and C. Svensson, “Power Consumption Estimation in CMOS VLSI Chips,” IEEE Journal of Solid-State Circuits, Vol. 29, No. 6, pp. 663–670, June 1994.CrossRefGoogle Scholar
  24. [24]
    A. Iyer and D. Marculescu, “Power Aware Microarchitecture Resource Scaling,” Proceedings of Design Automation and Test in Europe, pp. 190–196, March 2001.Google Scholar
  25. [25]
    A. Acquaviva, L. Benini and B. Ricco, “An Adaptive Algorithm for Low-Power Streaming Multimedia Processing,” Proceedings of Design Automation and Test in Europe, pp. 273–279, March 2001.Google Scholar

Copyright information

© Springer Science+Business Media New York 2002

Authors and Affiliations

  • Kiran Puttaswamy
    • 1
  • Lakshmi Narasimhan Chakrapani
    • 1
  • Kyu-Won Choi
    • 1
  • Yuvraj Singh Dhillon
    • 1
  • Utku Diril
    • 1
  • Pinar Korkmaz
    • 1
  • Kyoung-Keun Lee
    • 1
  • Jun Cheol Park
    • 1
  • Abhijit Chatterjee
    • 1
  • Peeter Ellervee
    • 2
  • Vincent John MooneyIII
    • 1
  • Krishna V. Palem
    • 1
  • Weng-Fai Wong
    • 3
  1. 1.School of Electrical and Computer EngineeringGeorgia Institute of TechnologyUSA
  2. 2.Department of Computer EngineeringTallinn Technical UniversityEstonia
  3. 3.School of ComputingNational University of SingaporeSingapore

Personalised recommendations