Abstract
Power consumption is an important dimension in microprocessor and digital system design. This is especially true in the embedded setting where microprocessors have to operate without the luxury of a large power supply or cooling structures. In this paper, we describe an infrastructure setup for the study of power-performance tradeoffs in microprocessor architecture and compiler optimizations. This infrastructure distinguishes itself from those already proposed in the literature in its use of power estimations based on synthesis of the architecture and the full integration of a well-established optimizing compiler framework. We present some preliminary results where we show how the circuit level and architectural techniques can be combined to save overall system power. In particular we reduce the clock frequency and supply voltage of level two memory accesses (circuit level technique) and compensate for the resulting increase in the completion time by implementing a non-blocking store buffer (architectural technique) resulting in up to 39% less power and up to 28% less energy on a set of candidate benchmarks.
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References
J. Montanaro, R.T. Witek, K. Anne,, A. J. Black, E. M. Cooper, D. W. Dobberpuhl, P. M. Donahue et. al., “A 160 Mhz 32 B 0.5 W CMOS RISC Microprocessor, ” IEEE journal of Solid-State Circuits, Vol. 31, No. 11, pp. 1703–1714, November 1996.
D. Seal, ARM Architecture Reference Manual, Second Edition, Addison Wesley Publications, England, 2001.D. Seal et. al., ARM Architecture Reference Manual, Addison Wesley Publications, 2001.
S. Furber, ARM System Architecture, First Edition, Addison Wesley Publications, England, 1996.
K. Ghose et. al., “Exploiting Bit-Slice Inactivities for Reducing Energy Requirements of Superscalar Processors,” Kool Chips workshop in association with MICRO33, Monterey, California, December 2000.
V. Tiwari and M. Tien-Chien Lee, “Power Analysis of a 32-bit Embedded Microcontroller,” Proceedings of the Asia and South Pacific Design Automation Conference, pp. 141–148, August 1995.
G. C. Cardarilli, M. Salmeri, A. Salsano and O.Simonelli, “Bus Architecture for Low Power VLSI Digital Circuits,” IEEE International Symposium on Circuit and Systems, pp. 21–24, May 1996.
B. Prince, Semiconductor Memories, Second Edition, John Wiley and Sons, England, 1996.
R. J. Evans and P. D. Franzion, “Energy Consumption Modeling and Optimization for SRAMs,” IEEE Journal of Solid State Circuits, Vol. 30, No. 5, pp. 571–579, May 1995.
Trimaran Consortium, http://www.trimaran.org
Synopsys, Inc., http://www.synopsys.com
LEDA Systems, Inc., http://www.ledasys.com
D. M. Pozar, Microwave Engineering, Second Edition, John Wiley & Sons Inc., USA, 1997.
http://www.eecs.umich.edu/;jringenb/power/
http://www.eecs.umich.edu/taustin/simplescalar
A. Chandrakasan and R. Brodersen, Low Power CMOS Design, John Wiley & Sons Inc., USA, 1998.
P. R. Panda and N. Dutt, “Low Power Memory Mapping through Reducing Address Bus Activity,” IEEE Transactions on VLSI Systems, Vol. 7, No. 3, pp. 309–320, September 1999.
N. Chang, K. Kim and H. G. Lee, “Cycle Accurate Energy Consumption Measurement and Analysis: Case Study of ARM7TDMI,” Proceedings of the International Symposium on Low Power Electronics and Design, pp. 185–190, July 2000.
A. Sinha, A. Wang and A. P. Chandrakasan, “Algorithmic Transforms for Efficient Energy Scalable Computation,” Proceedings of the International Symposium on Low Power Electronics and Design, pp. 31–36, July 2000.
M. Powell, S. Yang, B. Falsafi, K. Roy and T. N. Vijaykumar, “Gated Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories,” Proceedings of the International Symposium on Low Power Electronics and Design, pp. 90–95, July 2000.
Denalisoft, Inc., http://www.denalisoft.com
Compaq, Inc., http://www.compaq.com
http://www.trimaran.org/status.html.
D. Liu and C. Svensson, “Power Consumption Estimation in CMOS VLSI Chips,” IEEE Journal of Solid-State Circuits, Vol. 29, No. 6, pp. 663–670, June 1994.
A. Iyer and D. Marculescu, “Power Aware Microarchitecture Resource Scaling,” Proceedings of Design Automation and Test in Europe, pp. 190–196, March 2001.
A. Acquaviva, L. Benini and B. Ricco, “An Adaptive Algorithm for Low-Power Streaming Multimedia Processing,” Proceedings of Design Automation and Test in Europe, pp. 273–279, March 2001.
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Puttaswamy, K. et al. (2002). Power-Performance Trade-Offs in Second Level Memory Used by an ARM-Like RISC Architecture. In: Graybill, R., Melhem, R. (eds) Power Aware Computing. Series in Computer Science. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-6217-4_11
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DOI: https://doi.org/10.1007/978-1-4757-6217-4_11
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