A New Design Method for Self-Checking Unidirectional Combinational Circuits

  • V. V. Saposhnikov
  • A. Morosov
  • VL. V. Saposhnikov
  • M. Gössel
Part of the Frontiers in Electronic Testing book series (FRET, volume 11)


In this paper, a new method for the design of unidirectional combinational circuits is proposed. Carefully selected non-unidirectional gates of the original circuit are duplicated such that every single gate fault can only be propagated to the circuit outputs on paths with either an even or an odd number of inverters. Unlike previous methods, it is not necessary to localize all the inverters of the circuit at the primary inputs. The average area over head for the described method of circuit transformation is 16% of the original circuit, which is less than half of the area overhead of other known methods. The transformed circuits are monitored by Berger codes, or by the least significant two bits of a Berger code. All single stuck-at faults are detected by the method proposed.


Primary Input Area Overhead Combinational Circuit Benchmark Circuit Original Circuit 


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  1. 1.
    P.K. Lala, Fault Tolerant and Fault Testable Hardware Design, Prentice Hall, Englewood-Cliffs, N.J., 1985.Google Scholar
  2. 2.
    V.V. Saposhnikov and V1.V. Saposhnikov, “Self-Cheking Checkers for Balansed Codes,” Automation and Remote Control, Vol. 53, No. 3, Part 1, pp. 321–348, 1992.Google Scholar
  3. 3.
    V.V. Saposhnikov and VI.V. Saposhnikov, Self-Checking Discrete Circuits (in Russian), Energoatomizdat, St. Petersburg, 1992.Google Scholar
  4. 4.
    R.M. Sedmark, “Design for Self-Verification. An Approach for Dealing with Testability Problems in VLSI-Based Design,” Proc. 1979, Int. Test Conference, 1979, pp. 112–120.Google Scholar
  5. 5.
    S.K. Gupta and D.K. Pradhan, “Can Concurrent Checkers Help BIST?,” Proc. 1992 International Test Conference, 1992 pp. 140–150.Google Scholar
  6. 6.
    S. K. Gupta and D.K. Pradhan, “Utilization of On-line (Concurrent) Checkers during Built-in Self-Test and Vice Versa,” IEEE Trans. Computers, Vol. C-45, pp. 63–73, 1996.Google Scholar
  7. 7.
    E. Fujiwara, N. Muto, and K. Matsuoka, “A Self-Testing Group Parity Prediction Checker and its Use for Built-in-Testing,” IEEE Trans. Comp., Vol. C-33, No. 6, pp. 578–583, 1984.Google Scholar
  8. 8.
    T.R.N. Rao and E. Fujiwara, Error Control Coding for Computer Systems, Prentice Hall, 1989.Google Scholar
  9. 9.
    E.S. Sogomonyan, “Design of Built-in Self-Cheking Monitoring Circuits for Combinational Devices,” Automation and Remote Control, Vol. 35, No. 2, Part 2, pp. 280–289, 1974.Google Scholar
  10. 10.
    E. Fujiwara, “Self-Testing Group Parity Prediction Checker and its Use for Built-in-Testing,” Proc. 13th Test Symposium Fault Tolerant Computing, Milano, 1983, pp. 146–153.Google Scholar
  11. 11.
    M.J. Ashajee and S.M. Reddy, “On Totally Self-Checking Checkers for Separable Codes,” IEEE Trans. Comp., Vol. C-16, No. 8, pp. 737–744.Google Scholar
  12. 12.
    K. De, C. Natarajan, D. Nair, and P. Banerjee, “RSYN: A System for Automated Synthesis of Reliable Multilevel Circuits,” IEEE Transactions on Very Large Integration (VLSI) Systems, No. 2, pp. 186–195, 1994.CrossRefGoogle Scholar
  13. 13.
    A. Morosov, V.V. Saposhnikov, VLV Saposhnikov, and M. Gössel, “Self-Cheking Combinational Circuits with Unidirectionally Independent Outputs,” Technical Report Max-Planck Fault Tolerant Computing Group No. MPI-I-93–605, 1995, to be published in Journal of VLSI.Google Scholar
  14. 14.
    N.K. Jha and S.-J. Wang, “Design and Synthesis of Self-Checking VLSI Circuits,” IEEE Transaction CAD, Vol. 12, No. 6, pp. 878–887, 1993.Google Scholar
  15. 15.
    F.Y. Busaba and P.K. Lala, “Self-Checking Combinational Circuit Design for Single and Unidirectional Multibit Errors,” JETTA, No. 5, pp. 19–28, 1994.Google Scholar
  16. 16.
    E.S. Sogomonyan and M. Gössel, “Design of Self-Testing and On-Line Fault Detection Combinational Circuits with Weakly Independent Outputs,” JETTA, No. 4, pp. 267–281, 1993.Google Scholar
  17. 17.
    A. Bogliolo and M. Damiani, “Synthesis of Combinational Circuits with Special Fault-Handling Capabilities,” 13th IEEE Test Symposium, Princeton, N.J., 1995, pp. 454–459.Google Scholar
  18. 18.
    E.V. Slabakov, “Design of Totally Self-Checking Combinational Circuits by Use of Residual Codes,” Automation and Remote Control, Vol. 40, No. 10, Part 2, pp. 1333–1340, 1979.Google Scholar
  19. 19.
    M. Gössel and E.S. Sogomonyan, “Self-Parity Combinational Circuits for Self-Testing, Concurrent Fault Detection and Parity Scan Design,” IFIP Transactions A-42, Computer Science and Technology, VLSI-93, T. Yanagawa and P.A. Ivey ( Eds. ), North-Holland, 1994, pp. 103–111.Google Scholar
  20. 20.
    H. Fujiwara, Logic Testing and Design for Testability, The MIT Press Cambridge, Massachusetts, London, England, 1985.Google Scholar
  21. 21.
    J.P. Roth, W.G. Bouricius, and P.R. Schneider, “Programmed Algorithms to Compute Tests to Detect and Distinguish between Failures in Logic Circuits,” IEEE Trans., Vol. EC-16, No. 5, pp. 567–580, 1967.MathSciNetGoogle Scholar
  22. 22.
    M. Abramovici, M. Breuer, and H. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, New York, 1990.Google Scholar
  23. 23.
    E.M. Sentovich, K.J. Singh, L. Lavagno, C. Moon, R. Mur-gai, A. Saldanha, H. Savoj, P.R. Stephan, R.K. Brayton, and A. Sangiovanni-Vincentelli, “SIS: A System for Sequential Circuit Synthesis,” Electronics Research Laboratory, Memorandum No. UCB/ERL M92 /41, 1992.Google Scholar
  24. 24.
    K. De, C. Wu, and P. Banerjee, “Reliability Driven Logic Synthesis of Multilevel Circuits,” Int. Symp. on Circuits and Systems, pp. 1105–1108, 1992.Google Scholar
  25. 25.
    B. Bose and D.J. Lin, “Systematic Unidirectional Error-Detecting Codes,” IEEE Trans. Computers, Vol. C-34, pp. 1026–1032, 1985.Google Scholar
  26. 26.
    M.A. Marouf and A.D. Friedman, “Design of Self-Checking Checkers for Berger Codes,” Proc. 8th Annual Intern. Conf. on Fault Tolerant Computing, Toulouse, 1978, pp. 179–183.Google Scholar
  27. 27.
    E.S. Sogomonian, “Reliability of Self-Testing Using Functional Diagnostic Tools,” Automation and Remote Control, Vol. 49, No. 10, Part 2, pp. 1376–1380, 1988.Google Scholar

Copyright information

© Springer Science+Business Media New York 1998

Authors and Affiliations

  • V. V. Saposhnikov
    • 1
  • A. Morosov
    • 2
  • VL. V. Saposhnikov
    • 1
  • M. Gössel
    • 2
  1. 1.University for Railway-EngineeringSankt-PetersburgRussia
  2. 2.Institute for Informatik, Fault-Tolerant Computing GroupUniversity of PotsdamGermany

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