This chapter describes new techniques for the co-synthesis of real-time distributed embedded systems. Embedded system synthesis is co-synthesis because the hardware and software must be designed together to meet both performance and cost goals. In contrast to traditional distributed system design, we cannot assume that the topology of the distributed system is given. In contrast with previous work on hardware-software partitioning, we do not assume a fixed template such as a one-CPU-one-ASIC configuration. Our co-synthesis algorithm  selects the number of PEs, the type of each PE, as well as allocating functions to PEs and scheduling their execution. The co-synthesis algorithm is based on the analytic performance estimation algorithm presented in Chapter 4. The efficiency of the performance estimation algorithm allows us to quickly explore various architectures in a large design space.
The subproblems such as scheduling, allocation, or timing analysis on a fixed-architecture distributed system are NP-hard, let alone the overall architecture synthesis problem. Gupta  pointed out that timing is a global property and needs to be recalculated for the entire problem; it is why incremental circuit partition algorithms such as Kernighan-Lin heuristics  are not suitable for hardware-software partitioning when performance is taken into consideration. The characterization and constraints for embedded systems are frequently nonlinear; it is possible to model them by either integer linear programming (ILP) or mixed integer linear programming (MILP), but may introduce a lot of extra variables and constraints, which worsen the run time of the ILP solver.
Most co-synthesis algorithms proposed so far belong to either of the two categories: ILP formulation or incremental optimization heuristics. The ILP approach is very slow [45, 77]. The problem model characterized by an ILP formulation is usually difficult to extend. For example, when we want to improve an ILP formulation to handle rate constraints and preemptive scheduling, the size of the formulation may increase several times, which leads to an exponential growth of run time. The majority of the co-synthesis algorithms use incremental optimization heuristics.
Our algorithm co-synthesizes a heterogeneous distributed systems of arbitrary topology.
It balances multiple optimization criteria, including both delay and cost.
It takes into consideration both hard constraints and soft constraints in either delay or cost.
It performs preemptive scheduling under rate constraints during co-synthesis.
Heuristic techniques can be incorporated to help jump out of local minimum during optimization.
Section 5.2 uses performance estimates and the total system cost to compute a local sensitivity of the design to allocation of processes, based on the hard and soft deadlines as well as hard and soft cost constraints. Section 5.3 proposes a new priority prediction method to reschedule processes after every change of system architecture, according to the timing criticality of processes. Section 5.4 introduces a two-stage optimization strategy and a post processing method to avoid sub-optimal designs in some cases. Based on these techniques, Section 5.5 presents a gradient-search algorithm which simultaneously design the hardware engine and the application software architecture for performance and implementation cost. Section 5.6 gives the results of experiments with the algorithm.
Communication links will not be discussed in this chapter. Chapter 6 will extend the algorithms in this chapter to synthesize communication.
KeywordsMixed Integer Linear Programming Soft Constraint Hard Constraint Processor Utilization Task Graph
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