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Abstract

To produce high-quality and cost-effective multichip systems, they must be designed with test and fault diagnosis as critical design requirements. However, deciding on where and when to test and whether to apply Design For Test DFT) and Built-In Self-Test (BIST) at the IC, multichip module (MCM) or board level requires considerable study and evaluation to determine the economics of the various solutions and the payback. In this article we describe a tool called High Level Test Economics Advisor (Hi-TEA) that analyzes the economics of various test strategies for multichip designs at an early stage of the design cycle. The tool also allows the user to perform trade-off analysis on the impact of various cost, yield, or test effectiveness parameter on the final cost and quality of multichip designs. Experimental trade-off analysis data that were generated using the tool for some leading-edge multichip designs will also be presented.

Visiting researcher from Eastman Kodak Co.

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References

  1. Economics of Design and Test for Electronic Circuits and Systems, A.P. Ambler, M. Abadir, and S. Sastry, (eds.), Ellis Horwood Publisher, 1992, contains extended versions of papers presented at the First International Workshop on the Economics of Design and Test, Austin, Texas.

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  2. T.W. Williams and N.C. Brown, “Defect Level as a Function of Fault Coverage,” IEEE Pans. on Computers, vol. CO30, pp. 987–988, Dec. 1981.

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  3. C. Dislis, J. Dick, and A.P. Ambler, “An Economics Based Test Strategy Planner for VLSI Design,” Proceedings of the 2nd European Test Conference, 1991.

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  4. C. Dislis, A.P. A.bler, and J. Dick, “Economic Effects in Design and Test;’ IEEE Design and Test of Computers, vol. 6, Dec. 1991.

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© 1994 Springer Science+Business Media New York

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Abadir, M.S., Parikh, A.R., Bal, L., Sandborn, P.A., Murphy, C.F. (1994). High Level Test Economics Advisor (Hi-TEA). In: Abadir, M., Ambler, T. (eds) Economics of Electronic Design, Manufacture and Test. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-5048-5_6

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  • DOI: https://doi.org/10.1007/978-1-4757-5048-5_6

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-5142-7

  • Online ISBN: 978-1-4757-5048-5

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