Routing Switch Circuit Design
In commercial PLDs, buffers have recently replaced pass transistors as the preferred type of routing switch. This chapter investigates interconnect that mixes these two switch types together. The goals of this study are twofold: to reduce area by replacing a number of buffered switches with pass transistors and to reduce delay by allowing a signal to alternate between a buffer and a pass transistor switch. This is accomplished in three evolutionary steps. The first step is detailed transistor-level design of routing switches in 0.18µm technology. The second step is the evaluation of three new switch types which combine the advantages of two previously-used switch designs: they are nearly as fast under fanout as the fastest design, and they use less area than the smallest design. The third step is the evaluation of PLD architectures which mix buffers and pass transistors by replacing existing buffers with pass transistors.
KeywordsProgrammable Logic PMOS Transistor Benchmark Circuit Switch Type Delay Result
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