• Guy Lemieux
  • David Lewis


The rapid advancement of semiconductor technology has required the concurrent advancement of the digital systems design process. For example, early integrated circuits such as the Intel 4004 processor were completely hand-designed, including the layout artwork. This was a reasonable effort for a 2,300-transistor device built in 1971 with a 10µm technology process [Int02]. In contrast, the latest Intel Itanium 2 processor, released in July 2002, contains 220 million transistors in a 0.18µm process [Int02]. Designing such a large device requires hundreds of engineers who rely upon sophisticated CAD tools to manage the complexity. For the last five to ten years, each new Intel processor has been the pinnacle of design, setting the standard for other devices to follow. However, other new devices are reaching a similar level complexity. For example, the ATI Technologies RADEON 9700 graphics processor [ATIO2], also released in July 2002, is reported to contain 107 million transistors in a 0.15µm process [Aba02]. There is no doubt that increasingly larger devices will continue to be designed, so the demand for tools and design methodology advancement will continue as well.


Programmable Logic Interconnection Network Lookup Table Logic Cell Benchmark Circuit 


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  1. To compute the results in Table 1.1, twenty different benchmark circuits are placed and routed using the smallest PLD possible (with 20ß6 additional routing tracks). The architecture is a mesh-based PLD using a cluster with six 4-input LUTs. Half of the routing tracks are unbuffered and the other half are buffered only at alternate switching points. Even though this architecture contains very few buffers, routing area still dominates. The average area is determined by a geometric average across the benchmark circuits; the range is similarly determined by the minimum or maximum portion across the different circuits. The area data are compiled using the tools and methodology described later in Chapter 3.Google Scholar
  2. Area per logic cell includes a 4-input lookup table, a register, and all associated routing switches.Google Scholar
  3. A similar technique has been used in other work to design switch blocks [ZWC93], but not sparse crossbars.Google Scholar

Copyright information

© Springer Science+Business Media New York 2004

Authors and Affiliations

  • Guy Lemieux
    • 1
  • David Lewis
    • 2
    • 3
  1. 1.Department of Electrical and Computer EngineeringUniversity of British ColumbiaVancouverCanada
  2. 2.Altera Toronto Technology CentreAltera CorporationCanada
  3. 3.Edward S. Rogers Senior Department of Electrical and Computer EngineeringUniversity of TorontoTorontoCanada

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