# Defect Oriented Analog Testing

Chapter

## Abstract

Analog circuits due to their non-binary operation are influenced by process defects in a different manner compared to digital circuits. Seemingly an innocuous defect for digital logic may cause unacceptable degradation in analog circuit performance. This chapter surveys the advances in the field of defect oriented analog testing and summarizes strengths and weaknesses of the method for analog circuits.

## Keywords

Analog Circuit Test Vector Digital Circuit Fault Coverage Fault Simulation## Preview

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## References

- 1.B. Atzema, E. Bruts, M. Sachdev and T. Zwemstra, “Computer-Aided Testability Analysis for Analog Circuits,”
*Proceedings of the Workshop on Advances in Analog Circuit Design*, April 1995.Google Scholar - 2.R. Becker, et al., “PACT — A Programmable Analog CMOS Transmission Circuit for Electronic Telephone Sets,” Proceedings of European Solid State Circuits Conference, 1993, pp. 166–169.Google Scholar
- 3.F.P.M. Beenker, “Testability Concepts for Digital ICs,”
*Ph.D. Thesis, University of Twente*, Netherlands, 1994.Google Scholar - 4.R.S. Berkowitz, “Conditions for Network-element-value Solvability,”
*IRE Transactions on Circuit Theory*, vol. CAD-9, pp. 24–29, March 1962.MathSciNetGoogle Scholar - 5.E.M.J.G. Bruis, “Reliability Aspects of Defects Analysis,”
*Proceedings of European Test Conference, 1993*, pp. 17–26.Google Scholar - 6.E. Bruts, “Variable supply voltage testing for analogue CMOS and bipolar circuits,”
*Proceedings of International Test Conference*, 1994, pp. 562–571.Google Scholar - 7.P. Duhamel and J.C. Rault, “Automatic Test generation Techniques for Analog Circuits and Systems: A Review,”
*IEEE Transactions on Circuits and Systems*, vol. CAD-26, no. 7, pp. 411–440, July 1979.MathSciNetCrossRefGoogle Scholar - 8.N.J. Elias, “The Application of Statistical Simulation to Automated the Analog Test Development,”
*IEEE Transactions on Circuits and Systems*, vol. CAD-26, no. 7, pp. 513–517, July 1979.CrossRefGoogle Scholar - 9.B.R. Epstein, M. Czigler and S.R. Miller, “Fault Detection and Classification in Linear Integrated Circuits: An Application of Discrimination Analysis and Hypothesis Testing,”
*IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems*, vol. CAD-12, no. 1, pp. 102–112, January 1993.CrossRefGoogle Scholar - 10.R.J.A. Harvey, A.M.D. Richardson, E.M.J. Bruis and K. Baker, “Analogue Fault Simulation Based on Layout Dependent Fault Models,”
*Proceedings of International Test Conference*, 1994, pp. 641–649.Google Scholar - 11.C.F. Hawkins and J.M. Soden, “Electrical Characteristics and Testing Considerations for Gate Oxide Shorts in CMOS ICs”,
*Proceeding of International Test Conference*, 1985, pp. 544–555.Google Scholar - 12.G.J. Hemink, B.W. Meijer and H.G. Kerkhoff, “TASTE: A Tool for Analog System Testability Evaluation,”
*Proceeding of International Test Conference*, 1988, pp. 829–838.Google Scholar - 13.W. Hochwald and J.D. Bastian, “A DC Approach for Analog Dictionary Determination,”
*IEEE Transactions on Circuits and Systems*, vol. CAD-26, no. 7, pp. 523–529, July 1979.CrossRefGoogle Scholar - 14.H.H. Huston and C.P.Clarke, “Reliability Defect Detection and Screening During Processing — Theory and Implementation,”
*Proceedings of International Reliability Physics Symposium*, 1992, pp. 268–275.Google Scholar - 15.A.T. Johnson, Jr., “Efficient Fault Analysis in Linear Analog Circuits,”
*IEEE Transactions on Circuits and Systems*, vol. CAD-26, no. 7, pp. 475–484, July 1979.CrossRefGoogle Scholar - 16.F.C.M. Kuijstermans, M. Sachdev and L. Thijssen, “Defect Oriented Test Methodology for Complex Mixed-Signal Circuits,”
*Proceedings of European Design and Test Conference*, 1995, pp. 18–23.Google Scholar - 17.M. Mahoney, “
*DSP-Based Testing of Analog and Mixed-Signal Circuits*, Los Alamitos, California: IEEE Computer Society Press, 1987.Google Scholar - 18.W. Maly, F.J. Ferguson and J.P. Shen, “Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells,”
*Proceeding of International Test Conference*, 1984, pp. 390–399.Google Scholar - 19.W. Maly, W.R. Moore and A.J. Strojwas, “Yield Loss Mechanisms and Defect Tolerance,”
*SRC-CMU Research Center for Computer Aided Design, Dept. of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213.*Google Scholar - 20.W. Maly, A.J. Strojwas and S.W. Director, “VLSI Yield Prediction and Estimation: A Unified Framework,”
*IEEE Transactions on Computer Aided Design*, vol. CAD-5, no. 1, pp 114–130, January 1986.CrossRefGoogle Scholar - 21.W. Maly, “Realistic Fault Modeling for VLSI Testing,”
*24th ACM/IEEE Design Automation Conference, 1987*, pp.173–180.Google Scholar - 22.A. Meixner and W. Maly, “Fault Modeling for the Testing of Mixed Integrated Circuits,”
*Proceeding of International Test Conference*, 1991, pp. 564–572.Google Scholar - 23.R. Mehtani, B. Atzema, M. De Jonghe, R. Morren, G. Seuren and T. Zwemstra, “Mix Test: A Mixed-Signal Extension to a Digital Test System,”
*Proceedings of International Test Conference*, 1993, pp. 945–953.Google Scholar - 24.L. Milor and V. Visvanathan, “Detection of Catastrophic Faults in Analog Integrated Circuits,”
*IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems*, vol. CAD-8, pp. 114–130, February 1989.CrossRefGoogle Scholar - 25.L. Milor and A. Sangiovanni-Vincentelli, “Optimal Test Set Design For Analog Circuits”,
*International Conference on Computer Aided Design*,1990, pp. 294–297.Google Scholar - 26.N. Navid and A.N. Willson, Jr., “A Theory and an Algorithm for Analog Fault Diagnosis,”
*IEEE Transactions on Circuits and Systems*, vol. CAD-26, no. 7, pp. 440–456, July 1979.MathSciNetCrossRefGoogle Scholar - 27.A. Pahwa and R. Rohrer, “Band Faults: Efficient Approximations to Fault Bands for the Simulation Before Fault Diagnosis of Linear Circuits,”
*IEEE Transactions on Circuits and Systems*, vol. CAD-29, no. 2, pp. 81–88, February 1982.CrossRefGoogle Scholar - 28.M.J.M. Pelgrom and A.C. van Rens, “A 25 Ms/s 8-Bit CMOS ADC for Embedded Applications,”
*Proceedings 19th of European Solid State Circuits Conference*, 1993, pp. 13–16.Google Scholar - 29.R.J. van de Plassche, “
*Integrated Analog-to-Digital and Digital-to-Analog Converters*,” Dordrect: Kluwer Academic Publishers. 1994.Google Scholar - 30.R.W. Priester and J.B. Clary, “New Measures of Testability and Test Complexity for Linear Analog Failure Analysis,”
*IEEE Transactions on Circuits and Systems*, vol. CAD-28, no. 11, pp. 1088–1092, November 1981.CrossRefGoogle Scholar - 31.L. Rapisarda and R.A. Decarlo, “Analog Multifrequency Fault Diagnosis,”
*IEEE Transactions on Circuits and Systems*, vol. CAD-30, no. 4, pp. 223–234, April 1983.CrossRefGoogle Scholar - 32.R. Rodriguez-Montanes, E.M.J.G. Bruis and J. Figueras, “Bridging Defects Resistance Measurements in CMOS Process,”
*Proceeding of International Test Conference*, 1992, pp. 892–899.Google Scholar - 33.M. Sachdev, “Catastrophic Defect Oriented Testability Analysis of a Class AB Amplifier,”
*Proceedings of Defect and Fault Tolerance in VLSI Systems*, October 1993, pp. 319–326.Google Scholar - 34.M. Sachdev, “Defect Oriented Analog Testing: Strengths and Weaknesses,”
*Proceedings of 20th European Solid State Circuits Conference*, 1994, pp. 224–227.Google Scholar - 35.M. Sachdev, “A Defect Oriented Testability Methodology for Analog Circuits,”
*Journal of Electronic Testing: Theory and Applications*, vol. CAD-6, no. 3, pp. 265–276, June 1995.CrossRefGoogle Scholar - 36.M. Sachdev and B. Atzema, “Industrial Relevence of Analog IFA: A Fact or A Fiction,”
*Proceedings of International Test Conference*, 1995, pp. 61–70.Google Scholar - 37.M. Sachdev, “A DfT Method for Testing Internal and External Signals in AID Converters”,
*European patent application no*. 96202881. 7, 1996.Google Scholar - 38.R. Saeks, A. Sangiovanni-Vincentelli and V. Vishvanathan, “Diagnosability of Nonlinear Circuits and Systems-Part II: Dynamical
*case, IEEE Transactions on Circuits and Systems*, vol. CAD-28, no. 11, pp. 1103–1108, November 1981.CrossRefGoogle Scholar - 39.A.E. Salama, J.A. Starzyk and J.W. Bandler, “A Unified Decomposition Approach for Fault Location in Large Analog Circuits,”
*IEEE Transactions on Circuits and Systems*, vol. cas-31, no. 7, pp. 609–622, July 1984.MATHCrossRefGoogle Scholar - 40.J.P. Shen, W. Maly and F.J. Ferguson, “Inductive Fault Analysis of MOS Integrated Circuits,”
*IEEE Design and Test of Computers*, vol. cas-2, no. 6, pp. 13–26, 1985.Google Scholar - 41.M. Slamani and B. Kaminska, “Analog Circuit Fault Diagnosis Based on Sensitivity Computation and Functional Testing,”
*IEEE Design & Test of Computers*, vol. CAD-9, pp. 30–39, March 1992.CrossRefGoogle Scholar - 42.J.M. Soden and C.F. Hawkins, “Test Considerations for Gate Oxide Shorts in CMOS ICs,”
*IEEE Design & Test of Computers*, vol. cas-2, pp. 56–64, August 1986.CrossRefGoogle Scholar - 43.J.M. Soden and C.F. Hawkins, “Electrical Properties and Detection Methods for CMOS IC Defects,”
*Proceedings of European Test Conference*, 1989, pp. 159–167.Google Scholar - 44.M. Soma, “Fault Modeling and Test Generation for Sample and Hold Circuits,”
*Proceedings of International Symposium on Circuits and Systems*, 1991, pp. 2072–2075.Google Scholar - 45.M. Soma, “An Experimental Approach to Analog Fault Models,”
*Proceedings of Custom Integrated Circuits Conference*,1991, pp. 13.6.1–13.6.4.Google Scholar - 46.M. Soma, “A Design for Test Methodology for Active Analog Filters,”
*Proceedings of International Test Conference*, 1990, pp. 183–192.Google Scholar - 47.T.M. Souders and G.N. Stenbakken, “A Comprehensive Approach for Modeling and Testing Analog and Mixed Signal Devices,”
*Proceeding of International Test Conference*, 1990, pp. 169–176.Google Scholar - 48.H. Sriyananda and D.R. Towill, “Fault diagnosis Using Time-Domain Measurements,”
*Proceedings of Radio and Electronic Engineer*, vol. cas-9, no. 43, pp. 523–533, September 1973.CrossRefGoogle Scholar - 49.M. Syrzycki, “Modeling of Spot Defects in MOS Transistors,”
*Proceedings International Test Conference*, 1987, pp. 148–157.Google Scholar - 50.T.N. Trick, W. Mayeda and A.A. Sakla, “Calculation of Parameter Values from Node Voltage Measurements,”
*IEEE Transactions on Circuits and Systems*, vol. cas-26, no. 7, pp. 466–474, July 1979.MathSciNetCrossRefGoogle Scholar - 51.V. Vishvanathan and A. Sangiovanni-Vincentelli, “Diagnosability of Nonlinear Circuits and Systems-Part I: The DC
*case, IEEE Transactions on Circuits and Systems*, vol. cas-28, no. 11, pp. 1093–1102, November 1981.CrossRefGoogle Scholar - 52.K.D. Wagner and T.W. Williams, “Design for Testability of Mixed Signal Integrated Circuits,”
*Proceeding of International Test Conference*, 1988, pp. 823–828.Google Scholar - 53.A. Walker, W.E. Alexander and P. Lala, “Fault Diagnosis in Analog Circuits Using Elemental Modulation,”
*IEEE Design & Test of Computers*, vol. CAD-9, pp. 19–29, March 1992.Google Scholar - 54.H. Walker and S.W. Director, “VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits,”
*IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems*, vol. cas-5, pp. 541–556, October 1986.CrossRefGoogle Scholar - 55.R.H. Williams and C.F. Hawkins, “Errors in Testing,”
*Proceeding of International Test Conference*, 1990, pp. 1018–1027.Google Scholar

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© Springer Science+Business Media Dordrecht 1999