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Testing Defects in Programmable Logic Circuits

  • Manoj Sachdev
Part of the Frontiers in Electronic Testing book series (FRET, volume 10)

Abstract

Recent resurgence of programmable logic devices (PLDs) ushers a new era in digital system design. Modern PLD architectures offer flexibility of logic implementation. However, the same flexibility results in enormous test complexity. In this chapter, a brief review of testable PLD architecture is presented and methodologies for testing defects are outlined.

Keywords

Product Line Programmable Logic Test Pattern Fault Coverage Input Line 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media Dordrecht 1999

Authors and Affiliations

  • Manoj Sachdev
    • 1
  1. 1.Philips ResearchThe Netherlands

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