# Defect Oriented RAM Testing and Current Testable RAMs

## Abstract

RAMs are integral building blocks of modern ICs and systems. As far as the testing is concerned, RAMs suffer from quantitative issues of digital testing along with the qualitative issues of analog testing. This chapter reviews the state of the art of defect oriented testing of RAMs and proposes a RAM test methodology using I_{DDQ} and voltage based march tests. Bridging defects in a RAM matrix, including the gate oxide defects, are detected by four I_{DDQ} measurements. The I_{DDQ} test is then supplemented with voltage based march test to detect the defects (opens and data retention) not detectable by the I_{DDQ} technique. The combined test methodology reduces the algorithmic test complexity substantially.

## Keywords

Fault Model Test Algorithm Read Operation Open Defect NAND Gate## Preview

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## References

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