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Digital CMOS Fault Modeling and Inductive Fault Analysis

  • Manoj Sachdev
Part of the Frontiers in Electronic Testing book series (FRET, volume 10)

Abstract

We begin with an overview of digital fault models. Different fault models are classified according to the level of abstraction. The merits and shortcomings of these models are reviewed. The second half of the chapter is devoted to the defect oriented fault modeling methodology or Inductive Fault Analysis, as it is popularly known. Unlike the conventional fault modeling methods, IFA takes into account the circuit layout and manufacturing process defects to generate realistic and layout dependent faults.

Keywords

Fault Modeling Logic Gate Test Vector NAND Gate Delay Fault 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media Dordrecht 1999

Authors and Affiliations

  • Manoj Sachdev
    • 1
  1. 1.Philips ResearchThe Netherlands

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