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Storage Cycle Budget Distribution and Access Ordering

  • Francky Catthoor
  • Koen Danckaert
  • Chidamber Kulkarni
  • Erik Brockmeyer
  • Per Gunnar Kjeldsberg
  • Tanja Van Achteren
  • Thierry Omnes
Chapter

Abstract

In many cases, a fully customized (on-chip) memory architecture can give superior memory bandwidth and power characteristics over traditional hierarchical memory architecture including data caches. This is especially so when the application is very well analyzable at compile-time. In an embedded context this is typically quite well achievable because the application (set) to be mapped is usually fully fixed and the on-chip memory organisation can be at least partly tuned towards this application (set).

Keywords

Memory Access Asynchronous Transfer Mode Memory Bandwidth Flow Graph Storage Management 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 2002

Authors and Affiliations

  • Francky Catthoor
    • 1
  • Koen Danckaert
    • 1
  • Chidamber Kulkarni
    • 1
  • Erik Brockmeyer
    • 1
  • Per Gunnar Kjeldsberg
    • 2
  • Tanja Van Achteren
    • 3
  • Thierry Omnes
    • 1
  1. 1.IMECLeuvenBelgium
  2. 2.Norwegian Univ. of Sc. and Tech. (NTNU)TrondheimNorway
  3. 3.Katholieke Universiteit LeuvenLeuvenBelgium

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