Microelectronic packaging is the science of providing interconnections and a suitable operating environment for microelectronic circuits [1.1]. Packaging involves the critical activities of interconnecting, powering, cooling, and protecting semiconductor chips. The technologies, and materials available for microelectronic packaging are numerous. Figure 1.1 diagrams the electronic module assembly schemes in use today. All methods begin with chips (also referred to as bare die) and conclude with a completed module which could be interconnected within a larger system. The multiple levels shown in Figure 1.1 are often referred to as the packaging hierarchy. The number of levels within the hierarchy varies depending on the module assembly path chosen. Figure 1.1 does not show the complete packaging hierarchy. Traditionally, the complete hierarchy could include other elements such as a board or backplane level to which modules or cards are connected, a cable level (sometimes called gate level) in which boards are connected by cable, and a frame or box level which contains the entire system [1.1].
KeywordsConceptual Design Print Circuit Board Design Cycle Flip Chip Tradeoff Analysis
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- [1.1]Microelectronic Packaging Handbook, editors R. R. Tummala and E. J. Rymaszewski, Van Norstrand Reinhold, 1989.Google Scholar
- [1.2]D. P. Seraphim, C. Y. Li, and R. Lasky, Principles of Electronic Packaging, Design and Material Science, McGraw-Hill, 1989.Google Scholar
- [1.3]Multichip Module Technologies and Alternatives - The Basics, editors D. A. Doane and P. Franzon, Van Nostrand Reinhold, 1993.Google Scholar
- [1.4]C. F. Coombs, Printed Circuit Handbook, McGraw-Hill, 1988.Google Scholar
- [1.5]A. J. Prasad, Surface Mount Technology Principles and Practice, Van Norstrand Reinhold, 1989.Google Scholar
- [1.6]A. Kozak, C. Harris, K. Hubbard, J. Rostworowski, and I. Verigin, “MCMs in Telecommunications Designs,” Surface Mount Technology, vol. 5, no. 3, pp. 46–49, March, 1991.Google Scholar
- [1.7]R. O. Carlson, C. W. Eichelberger, R. J. Wojnarowski, L. M. Levinson, and J. E. Kohl, “A High-Density Copper/Polyimide Overlay Interconnection,” Proceedings of the Eighth International Electronics Packaging Conference, pp. 793–804, 1988.Google Scholar
- [1.8]Thin Film Multichip Modules,editors G. Messner, I. Turlik, J. W. Balde, and P. E. Garrow, ISHM Press, 1992.Google Scholar
- [1.9]J. W. Rozenblit, J. L. Prince, and O. A. Palusinski, “Towards a VLSI Packaging Design and Support Environment (PDSE) Concepts and Implementation,” Proceedings of the International Conference on Computer Design, pp. 443–448, 1990.Google Scholar
- [1.11]P. A. Sandborn and H. Hashemi, “A Design Advisor and Model Building Tool for the Analysis of Switching Noise is Multichip Modules,” Proceedings of the International Symposium on Microelectronics (ISHM), pp. 652–657, 1990.Google Scholar
- [1.12]ISO, EXPRESS Language Reference Manual, External Repre- sentation of Product Definition Data,” ISO TC184/SC4/WG5 N14, 1991.Google Scholar
- [1.13]P. A. Sandborn, K. Drake, and R. Ghosh, “Computer Aided Conceptual Design of Multichip Systems,” Proceedings of the Custom Integrated Circuits Conference, pp. 29.4.1–29.4.4, 1993.Google Scholar
- [1.15]W. P. Birmingham, A. P. Gupta, and D. P. Siewiorek, Automating the Design of Computer Systems, The MICON Project, Jones and Bartlett Publishers, 1992.Google Scholar