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Focal-Plane and Multiple Chip VLSI Approaches to CNNs

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Book cover Cellular Neural Networks and Analog VLSI

Abstract

In this paper, three alternative VLSI analog implementations of CNNs are described, which have been devised to perform image processing and vision tasks: a programmable low-power CNN with embedded photosensors, a compact fixed-template CNN based on unipolar current-mode signals, and basic CMOS circuits to implement an extended CNN model using spikes. The first two VLSI approaches are intended for focal-plane image processing applications. The third one allows, since its dynamics is defined by process-independent local ratios and its input/outputs can be efficiently multiplexed in time, the construction of very large multiple chip CNNs for more complex vision tasks.

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References

  1. L. O. Chua and L. Yang, “Cellular neural networks: Theory.” IEEE Transactions on Circuits and Systems 35 (10), pp. 1257–1272, Oct. 1988.

    Article  MathSciNet  MATH  Google Scholar 

  2. L. O. Chua and L. Yang, “Cellular neural networks: Applications” IEEE Transactions on Circuits and Systems 35 (10), pp. 1273–1290, Oct. 1988.

    Article  MathSciNet  Google Scholar 

  3. J. M. Cruz and L. O. Chua, “A CNN chip for connected component detection.” IEEE Transactions on Circuits and Systems 38 (7), pp. 812–816, July 1991.

    Article  Google Scholar 

  4. H. Harrer, J. A. Nossek, and R. Stelzl, “An analog implementation of discrete-time cellular neural networks” IEEE Transactions on Circuits and Systems 39 (3), pp. 466–476, May 1992.

    Google Scholar 

  5. A. Rodriguez Vazquez, S. Espejo, R. Dominguez Castro, J. L. Huertas, and E. Sanchez Sinencio, “Current-mode techniques for the implementation of continuous and discrete time cellular neural networks.” IEEE Transactions on Circuits and Systems Part 140 (3), pp. 132–146, March 1993.

    Google Scholar 

  6. J. E. Varrientos, E. Sanchez-Sinencio, and J. Ramirez-Angulo, “A current-mode cellular neural networks implementation.” IEEE Transactions on Circuits and Systems Part 140 (3), pp. 147–156, March 1993.

    Google Scholar 

  7. M. Anguita, F. J. Pelayo, A. Prieto, and J. Ortega, “Analog CMOS implementation of a discrete-time CNN with programmable cloning templates.” IEEE Transactions on Circuits and Systems Part 140 (3), pp. 215–219, March 1993.

    Google Scholar 

  8. S. Espejo, A. Rodriguez-Vazquez, R. Domínguez-Castro, J. L. Huertas, and E. Sanchez-Sinencio, “Smart-pixel cellular neural networks in analog current-mode CMOS technology.” IEEE Journal of Solid-State Circuits 29 (8), August 1994.

    Google Scholar 

  9. F. Sargeni and V. Bonaiuto, “High performance digitally programmable CNN chip with discrete templates,” in Proceedings of the CNNA-94, Rome, 1994, pp. 67–72.

    Google Scholar 

  10. A. Paasio, A. Dawidziuk, K. Halonen, and V. Porra, “Current mode cellular neural network with digitally adjustable template coefficients?’ in Proceedings Microneuro ‘84, IEEE Comp. Soc. Press., Turin, 1994, pp. 268–272.

    Google Scholar 

  11. R. Kinget and M. S. J. Steyaert, “A programmable analog cellular neural network CMOS chip for high speed image processing.” IEEE Journal of Solid-State Circuits 30 (3), March 1995.

    Google Scholar 

  12. S. Espejo, “VLSI design and modeling of CNNs,” PhD. Dissertation, University of Sevilla, March, 1994.

    Google Scholar 

  13. M. Anguita, F. J. Pelayo, F. J. Fernandez, and A. Prieto, “A low-power CMOS implementation of programmable CNNs with embedded photo-sensors” To appear in IEEE Transactions on Circuits and Systems Part I.

    Google Scholar 

  14. M. Anguita, F. J. Pelayo, E. Ros, D. Palomar, and A. Prieto, “VLSI implementations of CNNs for image processing and vision tasks: Single and multiple chip approaches,” invited talk at the 4th IEEE International Workshop on Cellular Neural Networks and their Applications, June, 1996.

    Google Scholar 

  15. T. Matsumoto, L. O. Chua, and H. Suzuki, “CNN cloning template: Connected component detector.” IEEE Transactions on Circuits and Systems 37, pp. 633–635, May 1990.

    Article  MathSciNet  Google Scholar 

  16. A. J. Schuler, M. Brabec, D. Shubel, and J. A. Nossek, “Hardware-oriented learning for cellular neural networks,” in Proceedings of CNNA-94, Rome, Italy, December 1994, pp. 183–188.

    Google Scholar 

  17. M. Anguita, “Implementación de arquitecturas VLSI para re-des neuronales celulares (CNNs),” Ph.D. Dissertation, Departamento de Electrónica y Tecnologia de Computadores, Universidad de Granada, June 1996.

    Google Scholar 

  18. A. Mortara and E. A. Vittoz, “A Communication Architecture Tailored for analog VLSI Artificial Neural Networks: Intrinsic Performance and Limitations.” IEEE Transactions on Neural Networks 5 (5), May 1994.

    Google Scholar 

  19. A. Mortara, A. E. Vittoz, and Ph. Venier, “A communication scheme for analog VLSI perceptive systems.” IEEE Journal of Solid State Circuits 30 (6), pp. 660–669, June 1995.

    Article  Google Scholar 

  20. F. J. Pelayo, E. Ros, R. Martin-Smith, F. J. Fernandez, and A. Prieto, “A VLSI approach to the implementation of additive and shunting neural networks?’ in Lecture Notes in Computer Science, Springer-Verlag, July 1995, vol. 930, pp. 728–735.

    Article  Google Scholar 

  21. F. J. Pelayo, E. Ros, X. Atreguit, and A. Prieto, “A bio-inspired VLSI neural model using spikes.” Sent to Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers.

    Google Scholar 

  22. X. Aneguit and E. A. Vittoz, “Perception systems implementation in analog VLSI for real-time applications,” in Proceedings of the PerAc’94, Lausanne, Switzerland, 1994, pp. 170–180.

    Google Scholar 

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© 1998 Springer Science+Business Media New York

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Anguita, M., Pelayo, F.J., Ros, E., Palomar, D., Prieto, A. (1998). Focal-Plane and Multiple Chip VLSI Approaches to CNNs. In: Chua, L.O., Gulak, G., Pierzchala, E., Rodríguez-Vázquez, A. (eds) Cellular Neural Networks and Analog VLSI. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-4730-0_4

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  • DOI: https://doi.org/10.1007/978-1-4757-4730-0_4

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-5030-7

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