The outcome of the architecture exploration phase is an architectural model at the level of register transfer (RT) accuracy. This model is appropriate to optimize and benchmark the architecture in terms of throughput and resource requirements. However, to get meaningful data on hardware cost and performance parameters (e.g. design size, power consumption, clock frequency) the processor model has to be taken through the standard synthesis flow. By definition, the LISA language targets the description of programmable architectures in terms of their instruction-set, behavior, and structure. Detailed hardware structures are not modeled for the complete architecture as this would contradict the idea of generating fast instruction-set simulators (cf. chapter 2.1). On the level of RT accurate LISA models this concerns especially the description of the instruction decoding procedure, processor control, and behavioral code which is still carried out in an abstract way.
KeywordsHardware Description Language Embed Processor Target Architecture Architecture Implementation CORE Architecture
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