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Placement

  • Koen Lampaert
  • Georges Gielen
  • Willy Sansen
Chapter
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 501)

Abstract

This chapter addresses the placement problem for high-performance analog circuits. The placement phase is crucial for the performance degradation of an analog circuit layout since it influences all the parasitic layout effects which have been discussed in chapter 2. The distance between matching devices, and therefore also their matching degree is determined during placement. The placement of a circuit also determines its thermal profile. In addition, it greatly influences the values of the interconnect parasitics. Although their final values are determined during routing, their minimum values are fixed by the configuration of the device terminals, which is determined during placement. A performance driven placement algorithm therefore has to take into account all of these performance degrading effects simultaneously.

Keywords

Simulated Annealing Discrete Cosine Transform Minimum Span Tree Simulated Annealing Algorithm Analog Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 1999

Authors and Affiliations

  • Koen Lampaert
    • 1
  • Georges Gielen
    • 1
  • Willy Sansen
    • 1
  1. 1.Katholieke Universiteit LeuvenBelgium

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