VLSI Implementation: Search Engine II (1D Array)
This chapter describes the VLSI implementation of a flexible motion estimation (ME) accelerator for low-power portable video real-time encoding applications. For low-power motion estimation the main design aim was to optimize the VLSI-architecture for low on-chip memory bandwidth, as the memory access bandwidth is directly related to power consumption. The second design goal was to take into account a low number of memory modules (or memory ports), cf. section 6.3.4. The presented VLSI architecture “Search Engine II”, [Kuhn 99], supports, besides the exhaustive search motion estimation, several ME algorithms with reduced computational complexity, in order to meet computational demands and power consumption requirements.
KeywordsMotion Estimation Clock Cycle Search Area Current Block VLSI Architecture
Unable to display preview. Download preview PDF.
- [Cheng 96].K.W. Cheng, S.C. Chan: “Fast block matching algonthms for motion estimation”, ICASSP 96, 1996,p 2318ffGoogle Scholar
- [Dut 96].Santanu Dutta and Wayne Wolf: “A Flexible Parallel Architecture Adapted to Block-Matching Motion-Estimation Algonthms”, IEEE Transactions on Circuits and Systems for Video Technology, vol. 6, no. 1, feb 1996, pp 74–86Google Scholar
- [Dut 98].Santanu Dutta, Wayne Wolf, Andrew Wolfe: “A methodology to evaluate memory architecture design tradeoffs for video signal processors”, IEEE Transactions on Circuits and Systems for Video Technology, vol. 8, no. 1, feb 1998, pp. 36–53Google Scholar
- [Kuhn 99].Kuhn P., Niedermeier U., Chao L.-F., Stechele W.: “A flexible low power VLSI architecture for MPEG-4 motion estimation”, vol. SPIE 3653 Visual Communications and Image Processing, San Jose, Jan. 1999Google Scholar
- [NEC 98].NEC Electronics: “CBC-C 10 Family, 0.25..im Cell-Based IC - preliminary user’s manual”, n.p., January 1998Google Scholar
- [SPARC].Internet: http://www.sun.com/microelectionics/products/microc.html