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Design Space Motion Estimation Architectures

  • Peter Kuhn
Chapter

Abstract

In this chapter motion estimation architectures are evaluated for the requirements of the visual (video) part of the MPEG-4 standard. Due to the very complex nature of the design space for motion estimation VLSI architectures, there are numerous VLSI architectures and design trade-offs. Proper consideration of these trade-offs can lead to an optimal VLSI architecture design for a selected motion estimation (ME) algorithm or a number of selected motion estimation algorithms under particular application constraints. The aim of this chapter is to evaluate block-matching motion estimation algorithms from a hardware point of view for MPEG-4. This is in contrast to the previous chapter where the block-matching algorithms were evaluated in terms of number of operations and memory bandwidth for software implementation on a programmable processor. It will be shown that the commonly used complexity metric of the number of operations for a processor implementation is not suitable for VLSI implementations.

Keywords

Motion Estimation Clock Cycle Memory Bandwidth VLSI Architecture VLSI Implementation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media Dordrecht 1999

Authors and Affiliations

  • Peter Kuhn
    • 1
  1. 1.Technical University of MunichGermany

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