High-speed A/D converters
The best-known architecture for a high-speed analog-to-digital converter is the flash converter structure. In this structure an array of comparators compares the input voltage with a set of increasing reference voltages. The comparator outputs represent the input signal in a digital (thermometer) code which can be easily converted into a Gray or binary weighted output code. The flash architecture shows a good speed performance and can easily be implemented in an integrated circuit as a repetition of simple comparator blocks and a (ROM) decoder structure. However, this architecture requires 2 N -1 comparators to achieve an N-bit resolution. The parallel structure makes it difficult to obtain a high-resolution while maintaining at the same time a large bandwidth, a low power consumption, and a small die size. Interpolation between reference levels reduces the number of reference taps and input amplifiers resulting in a lower power consumption. The influence of offset voltages in the input amplifiers can be reduced by using averaging between active amplifier stages. At the same time, signal-to-noise ratio is improved without using more power. An alternative to the full-flash architecture is the multi-step A/D conversion or sub ranging principle. In highspeed converters the two-step architecture is the most popular because of the ease of implementation. However, a two-step architecture must be preceded by a sample-and-hold amplifier which performs the sampling of the analog input signal. In the two-step architecture a coarse and fine quantization takes place. These succeeding conversion steps need time. The sample-andhold operation on the signal keeps the sampled signal constant. During this “hold” time the conversion takes place, making it virtually “timeless.” After the coarse quantization is performed, the digital signal is applied to a D/A converter to reconstruct the analog signal. This reconstructed signal is subtracted from the analog input signal which is held by the sample-andhold amplifier. After subtraction has taken place the residue signal can be amplified and is then applied to the fine quantizer which performs the conversion into a digital value. The coarse plus fine output code with, in many cases, an error correction operation results in the final digital output word. A good balance between circuit complexity, power consumption, and die size is obtained in this type of converter. The final dynamic performance, however, depends substantially on the quality and dynamic performance of the sample-and-hold amplifier.
KeywordsReference Voltage Gray Code Differential Pair Output Code Input Amplifier
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