Abstract
After placement, the positions and the sizes of all cells and large IP blocks are determined. The task for the following step, routing, is to connect the cells and IP blocks by metal wires, according to the netlist information, under the constraints of the design rules and timing requirements.
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References
International Technology Roadmap for Semiconductors, 2001 Edition http: / /public.itrs.net/Files/2001ITRS/Home.htm
S. Akers (1967) A modification of Lee’s path connection algorithm. IEEE Trans. on Computers, vol. EC-16, pages 97–98.
J. Soukup. (1978) Fast maze router. In Proc. 15th Design Automation Conference, pages 100–102.
K. Mikami and K. Tabuchi. (1968) A computer program for optimal routing of printed circuit connectors. In Proc. IFIPs, vol. H-47, pages 1475–1478.
D. Hightower. (1969) A solution to line routing problems on the continuous plane. In Proc. IEEE 6th Design Automation workshop, pages 1–24.
R. Nair. (1987) A simple yet effective technique for global wiring. IEEE Trans. on Computer-Aided Design, CAD-6(2).
L. McMurchie and C. Ebeling. (1995) Pathfinder: a negotiation-based performance-driven router for FPGAs. In Proc. 3rd International ACM/SIGDA Symposium on Field-Programmable Gate Arrays, pages 111–117.
R. Carden, J. Li, and C.-K. Cheng. (1996) A global router with a theoretical bound on the optimal solution. IEEE Trans. Computer-Aided Design, vol. 15, pages 208–216.
C. Albrecht. (2000) Provably good global routing by a new approximation algorithm for multicommodity flow. In Proc. International Symposium on Physical Design, page 19–25.
J. Cong and P. Madden. (1998) Performance driven multi-layer general area routing for PCB/MCM designs. In Proc. 35th Design Automation Conference, pages 356–361.
J. Cong, L. He, C.-K. Koh, and P. Madden. (1996) Performance optimization of VLSI interconnect layout. Integration, the VLSI journal, vol. 21, no. 1–2, pages 1–94.
C. Chang and J. Cong. (2000) Pseudo pin assignment with crosstalk noise control. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, pages 598–611.
J. Cong, J. Fang, K. Khoo. (Apr 2000) DUNE: A multi-layer gridless routing system with wire planning. In Proc. International Symposium on Physical Design, pages 12–18.
M. Burstein and R. Pelavin. (1983) Hierarchical channel router. In Proc. of 20th Design Automation Conference, pages 519–597.
J. Heisterman and T. Lengauer. (1991) The efficient solution of integer programs for hierarchical global routing. IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, vol. 10, pages 748–753.
D. Wang and E. Kuh. (Feb 1997) A new timing driven multiplayer MCM/IC routing algorithm. In Proc. IEEE Multi-Chip module Conference, pages 89–94.
G. Karypis, R. Aggarwal, V. Kumar, and s. Shekhar. (1999) Multilevel hypergraph partitioning: Applications in VLSI domain. IEEE Trans. on Very large Scale Integration Systems, vol. 7, pages 69–79.
J. Cong, S. Lim, and C. Wu. (2000) Performance driven multilevel and multiway partitioning with retiming. In Proc. 37th Design Automation Conference, pages 274–279.
T. Chan, J. Cong, T. Kong, and J. Shinnerl. (Nov 2000) Multilevel optimization for large-scale circuit placement. In Proc. IEEE International Conference on Computer Aided Design, pages 171–176.
J. Cong, J. Fang and Y. Zhang. (Nov 2001) Multilevel Approach to Full-Chip Gridless Routing. In Proc. IEEE International Conference on Computer Aided Design, pages 396–403.
J. Cong, M. Xie and Y. Zhang. (Nov 2002) An Enhanced Multilevel Routing System. Accepted by IEEE International Conference on Computer Aided Design.
C. Chiang, M. Sarrafzadeh, and C.K Wong. (Nov 1989) A powerful global router: Based on Steiner min-max trees. In Proc. IEEE International Conference on Computer-Aided Design, pages 2–5.
C. Chiang, M. Sarrafzadeh, and C.K. Wong. (1992) A weighted-Steinertree-based global router. Manuscript.
J. Cong, A. B. Kahng and K.-S. Leung. (1999) Efficient algorithms for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 1, pages 24–39.
J. Cong, J. Fang, K. Khoo. (Nov 1999) An implicit connection graph maze routing algorithm for ECO routing. In Proc. International Conference on Computer Aided Design, pages 163–167.
M. Borah, R.M. Owens, M.J. Irwin. (1994) “An edge-based heuristic for Steiner routing. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 12, pages 1563–1568.
J. Griffith, G. Robins, J.S. Salowe, T. Zhang. (1994) Closing the gap: near-optimal Steiner trees in polynomial time. IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, vol. 13, no. 11, pages 1351–1365.
J. Cong and X. Yuan. (2000) Routing tree construction under fixed buffer locations. In Proc. 37th Design Automation Conference, pages 379–384.
N. Garg and J. Konemann. (Nov 1998) Faster and simpler algorithms for multicommodity flow and other fractional packing problems. In Proc. Annual Symposium on Foundations of Computer Science, pages 300–309.
R. Karp, F. Leighton, R. Rivest, C. Thompson. (1987) U. Vazirani, and V. V. Vazirani. Global wire routing in two-dimensional arrays. Algorithmica, vol. 2, pages 113–129.
E. Dijkstra. (1959) A note on two problems in connexion with graphs. Numerische Mathematik, vol. 1, pages 269–271.
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Cong, J., Xie, M., Zhang, Y. (2003). Multilevel VLSI Routing. In: Cong, J., Shinnerl, J.R. (eds) Multilevel Optimization in VLSICAD. Combinatorial Optimization, vol 14. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-3748-6_5
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