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High-order Cascade Multi-bit ΣΔ Modulators

  • F. Medeiro
  • R. del Río
  • J. M. de la Rosa
  • B. Pérez-Verdú
  • A. Rodríguez-Vázquez
Chapter

Abstract

Motivated by the commercial success of the wireline communication products, mixed-signal designers are being pushed to integrate A/D and D/A interfaces featuring 12- to 16-bit effective resolution for signal bandwidths well in excess of 1MHz [1]. These specifications must be achieved in a low-voltage scenario, making use of poor performance (and often badly characterized) devices, which decreases the “analog speed” of deep-submicron CMOS processes.

Keywords

Quantization Error Integrator Weight Input Transistor Unitary Capacitor Capacitor Mismatch 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 2003

Authors and Affiliations

  • F. Medeiro
  • R. del Río
  • J. M. de la Rosa
  • B. Pérez-Verdú
  • A. Rodríguez-Vázquez

There are no affiliations available

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