The (CMOS) semiconductor industry has continued to prosper since the early 70s. The ever decreasing feature size has provided improved functionality at a reduced cost. As the feature size decreases, designs move from digital microprocessors and application-specific integrated circuits (ASICs) to systems-on-a-chip (SoC). Especially the wired (broadband) and wireless voice and data communications as well as the consumer market push integration of complete systems on a single die to reduce cost. The ITRS report from 1999 though reported that design productivity is lagging behind. With a productivity growth rate of only 21%, compared to 58% complexity growth rate, design cost is increasing rapidly. For analog and/or mixed-signal design the situation is even worse because of the lack of commercial EDA tools to support the analog design. Productivity should be boosted to double every year in order to bridge the gap [ITRS 01], but remedies are not clear, in particular for analog and RF design.
KeywordsDesign Time Analog Design Systematic Design Methodology Presented Test Case Decrease Feature Size
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