Clock Tree Design Flow in ASIC

Abstract

This chapter shows the clock tree design flow in the timing optimised layouts based on the place and route CAD tools [61]. It shows one example of automation CAD tools used for the clock network design. The chapter is organized in six sections. Section 11.1 introduces the flow overview of the clock tree synthesis. Section 11.2 shows the detailed commands for clock buffer synthesis. Section 11.3 presents the commands to report the skew and clock tree topology. Section 11.4 describes the commands to route the clock net. Section 11.5 shows the commands to verify the clock skew after the clock net is routed.