Non-Hanan Optimization for Global VLSI Interconnect
Under current Very Large Scale Integration (VLSI) technology, tens of millions of transistors can be integrated on a single chip, and future trends show that circuit sizes will continue to increase exponentially. Under this scenario, the performance bottleneck will shift to the delays associated with the metal wires, or interconnect, used to join these transistors. In the future, as transistor feature sizes become progressively smaller, the switching speed of a transistor driving a minimum load will become faster. On the other hand, as interconnect wires become thinner and longer, the interconnect delay for global wires is projected to increase, relative to the gate delay, due to the increased wire resistance. Both trends lead interconnect delay to dominate logic delay and become a significant bottleneck in VLSI system performance . As a result, many efforts have been carried out in recent years to improve the interconnect performance, and a good overview of these works is provided in [2–4].
KeywordsSteiner Tree Steiner Point Very Large Scale Integration Wire Length Buffer Space
Unable to display preview. Download preview PDF.
- J. Cong, “Challenges and opportunities for design innovations in nanometer technologies.” SRC Design Sciences Concept Paper, 1997.Google Scholar
- C.-K. Cheng, J. Lillis, S. Lin, and N. Chang, Interconnect analysis and synthesis. New York, NY: Wiley Interscience, 2000.Google Scholar
- S. S. Sapatnekar, “RC interconnect optimization under the Elmore delay model,” in Proceedings of the ACM/IEEE Design Automation Conference, pp. 392–396, 1994.Google Scholar
- J. Cong and C. K. Koh, “Interconnect layout optimization under higher-order RLC model,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 713–720, 1997.Google Scholar
- R. Gupta, B. Krauter, B. Tutuianu, J. Willis, and L. T. Pileggi, “The Elmore delay as a bound for RC trees with generalized input signals,” in Proceedings of the ACM/IEEE Design Automation Conference, pp. 364–369, 1995.Google Scholar
- J. Rubinstein, P. Penfield, and M. A. Horowitz, “Signal delay in RC tree networks,” IEEE Transactions on Computer-Aided Design, vol. CAD-2, pp. 202–211, July 1983.Google Scholar
- C. L. Ratzlaff, N. Gopal, and L. T. Pillage, “RICE: Rapid interconnect circuit evaluator,” in Proceedings of the ACM/IEEE Design Automation Conference, pp. 555–560, 1994.Google Scholar
- C. C. N. Chu and D. F. Wong, “Closed form solution to simultaneous buffer insertion/sizing and wire sizing,” in Proceedings of the ACM International Symposium on Physical Design, pp. 192–197, 1997.Google Scholar
- N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI design: a systems perspective. Reading, MA: Addison-Wesley Publishing Company, 1993.Google Scholar