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Non-Hanan Optimization for Global VLSI Interconnect

  • Jiang Hu
  • Sachin S. Sapatnekar
Part of the Network Theory and Applications book series (NETA, volume 8)

Abstract

Under current Very Large Scale Integration (VLSI) technology, tens of millions of transistors can be integrated on a single chip, and future trends show that circuit sizes will continue to increase exponentially. Under this scenario, the performance bottleneck will shift to the delays associated with the metal wires, or interconnect, used to join these transistors. In the future, as transistor feature sizes become progressively smaller, the switching speed of a transistor driving a minimum load will become faster. On the other hand, as interconnect wires become thinner and longer, the interconnect delay for global wires is projected to increase, relative to the gate delay, due to the increased wire resistance. Both trends lead interconnect delay to dominate logic delay and become a significant bottleneck in VLSI system performance [1]. As a result, many efforts have been carried out in recent years to improve the interconnect performance, and a good overview of these works is provided in [2–4].

Keywords

Steiner Tree Steiner Point Very Large Scale Integration Wire Length Buffer Space 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    J. Cong, “Challenges and opportunities for design innovations in nanometer technologies.” SRC Design Sciences Concept Paper, 1997.Google Scholar
  2. [2]
    A. B. Kahng and G. Robins, On optimal interconnections for VLSI. Boston, MA: Kluwer Academic Publishers, 1995.MATHCrossRefGoogle Scholar
  3. [3]
    J. Gong, L. He, C.-K. Koh, and P. H. Madden, “Performance optimization of VLSI interconnect layout,” Integration: the VLSI Journal, vol. 21, pp. 1–94, 1996.CrossRefGoogle Scholar
  4. [4]
    C.-K. Cheng, J. Lillis, S. Lin, and N. Chang, Interconnect analysis and synthesis. New York, NY: Wiley Interscience, 2000.Google Scholar
  5. [5]
    S. S. Sapatnekar, “RC interconnect optimization under the Elmore delay model,” in Proceedings of the ACM/IEEE Design Automation Conference, pp. 392–396, 1994.Google Scholar
  6. [6]
    J. Cong and C. K. Koh, “Interconnect layout optimization under higher-order RLC model,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 713–720, 1997.Google Scholar
  7. [7]
    H. Hou, J. Hu, and S. S. Sapatnekar, “Non-Hanan routing,” IEEE Transactions on Computer-Aided Design, vol. 18, pp. 436–444, Apr. 1999.CrossRefGoogle Scholar
  8. [8]
    M. Hanan, “On Steiner’s problem with rectilinear distance,” SIAM Journal on Applied Mathematics, vol. 14, no. 2, pp. 255–265, 1966.MathSciNetMATHCrossRefGoogle Scholar
  9. [9]
    J. Hu and S. S. Sapatnekar, “Algorithms for non-Hanan-based optimization for VLSI interconnect under a higher order AWE model,” IEEE Transactions on Computer-Aided Design, vol. 19, pp. 446–458, Apr. 2000.CrossRefGoogle Scholar
  10. [10]
    W. C. Elmore, “The transient response of damped linear networks with particular regard to wideband amplifiers,” Journal of Applied Physics, vol. 19, pp. 55–63, Jan. 1948.CrossRefGoogle Scholar
  11. [11]
    K. D. Boese, A. B. Kahng, B. A. McCoy, and G. Robins, “Near-optimal critical sink routing tree constructions,” IEEE Transactions on Computer-Aided Design, vol. 14, pp. 1417–36, Dec. 1995.CrossRefGoogle Scholar
  12. [12]
    L. T. Pillage and R. A. Rohrer, “Asymptotic waveform evaluation for timing analysis,” IEEE Transactions on Computer-Aided Design, vol. 9, pp. 352–366, Apr. 1990.CrossRefGoogle Scholar
  13. [13]
    J. Qian, S. Pullela, and L. T. Pillage, “Modeling the effective capacitance for the RC interconnect of CMOS gates,” IEEE Transactions on Computer-Aided Design, vol. 13, pp. 1526–1535, Dec. 1994.CrossRefGoogle Scholar
  14. [14]
    R. Gupta, B. Krauter, B. Tutuianu, J. Willis, and L. T. Pileggi, “The Elmore delay as a bound for RC trees with generalized input signals,” in Proceedings of the ACM/IEEE Design Automation Conference, pp. 364–369, 1995.Google Scholar
  15. [15]
    J. Rubinstein, P. Penfield, and M. A. Horowitz, “Signal delay in RC tree networks,” IEEE Transactions on Computer-Aided Design, vol. CAD-2, pp. 202–211, July 1983.Google Scholar
  16. [16]
    C. L. Ratzlaff, N. Gopal, and L. T. Pillage, “RICE: Rapid interconnect circuit evaluator,” in Proceedings of the ACM/IEEE Design Automation Conference, pp. 555–560, 1994.Google Scholar
  17. [17]
    C. C. N. Chu and D. F. Wong, “Closed form solution to simultaneous buffer insertion/sizing and wire sizing,” in Proceedings of the ACM International Symposium on Physical Design, pp. 192–197, 1997.Google Scholar
  18. [18]
    J. Cong and B. Preas, “A new algorithm for standard cell global routing,” Integration: the VLSI Journal, vol. 14, no. 1, pp. 49–65, 1992.MATHCrossRefGoogle Scholar
  19. [19]
    N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI design: a systems perspective. Reading, MA: Addison-Wesley Publishing Company, 1993.Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 2001

Authors and Affiliations

  • Jiang Hu
    • 1
  • Sachin S. Sapatnekar
    • 1
  1. 1.Department of Electrical and Computer EngineeringUniversity of MinnesotaMinneapolisUSA

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