As the seemingly simple and straightforward problem of weighted-sum computation was approached, its multiple facets started unfolding. Several optimization opportunities were identified in the area-delay-power space targeted to technologies ranging from programmable processors to hardwired implementations with or without a hardware multiplier. The algorithmic and architectural transformations presented in this book cover this entire solution space.
KeywordsPower Dissipation Residue Number System High Level Synthesis Data Flow Graph Dynamic Power Management
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