• Francis Balestra
  • Gérard Ghibaudo


The SOI CMOS is shown in Fig. 1. A buried insulator, which is typically an oxide layer, is fabricated in the silicon substrate using various methods (see next paragraph).


Threshold Voltage Gate Oxide Subthreshold Swing Double Gate Drain Bias 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    J. P. Colinge, Silicon-On-Insulator technology: materials to VLSI. Kluwer Academic Publishers, 1991.Google Scholar
  2. 2.
    S. Cristoloveanu and S. S. Li, Electrical characterization of Silicon-On-Insulator materials and devices. Kluwer Academic Publishers, 1995.Google Scholar
  3. 3.
    M. Watanabe and A. Tooi, Formation of SiO2 films by oxygen-ion bombardment, Jap. J. Appl. Phys., 5, p. 737, 1966.CrossRefGoogle Scholar
  4. 4.
    K. Izumi, M. Doken, and H. Ariyoshi, CMOS devices fabricated on buried SiO2 layers formed by oxygen implantation into silicon, Electronics Lett., 14, p. 593, 1978.CrossRefGoogle Scholar
  5. 5.
    J. Margail, I. Stoemenos, C. Jaussaud, M. Dupuy, P. Martin, B. Blanchard, and M. Bruel, Structural characterization of SIMOX structures », in Energy Beam Solid Interactions and Transient Thermal Processing, V. T. Nguyen and A. G. Cullis eds., Les Editions de Physique, Les Ulis, France, p. 519, 1986.Google Scholar
  6. 6.
    K. Mitani and U. M. Gösele, Wafer bonding technology for silicon-on-insulator applications: a review, J. Electronic Materials, 21, p. 669, 1992.CrossRefGoogle Scholar
  7. 7.
    P. B. Mumola, G. J. Gardopee, P. J. Clapis, C. B. Zarowin, L. D. Bollinger, and A. M. Ledger, Plasma thinned SOI bonded wafers, IEEE Int. SOI Conf. Proc, p. 152, 1992.Google Scholar
  8. 8.
    M. Bruel, Electronics Lett., 31, p. 1201, 1995.CrossRefGoogle Scholar
  9. 9.
    F. Balestra, J. Brini, and P. Gentil, Simulation of deep depleted SOI MOSFETs with back potential control, Proc. ESSDERC’84, Lille, France, 1984, in Physica 129B, p. 296, 1985. F. Balestra, J. Brini, and P. Gentil, Comparison between experiment, analytical models and numerical simulation for threshold voltages of deep depleted SOI MOSFETs, Proc. ESSDERC’85, Aachen, Germany, p. 232, 1985.Google Scholar
  10. 10.
    J. P. Colinge, Subthreshold slope of thin-film SOI MOSFET’s, IEEE Electron Dev. Lett., EDL-7, p. 244, 1986.CrossRefGoogle Scholar
  11. 11.
    F. Balestra, G. Ghibaudo, M. Benachir, and J. Brini, Analytical modelling of single and double gate thin film SOI MOSFET’s, Proc. ESSDERC’89 (Berlin, Germany, Sept. 89), Sringer-Verlag, p. 889, 1989.Google Scholar
  12. 12.
    F. Balestra, M. Benachir, J. Brini, and G. Ghibaudo, Analytical models of subthreshold swing and threshold voltage for thin-and ultra-thin-film SOI MOSFET’s, IEEE Trans. Electron Dev., ED-37, p. 2303, 1990CrossRefGoogle Scholar
  13. 13.
    D. J. Wouters, J. P. Colinge, and H. E. Maes, IEEE Trans. Electron Devices, ED-37, p. 2022, 1990.CrossRefGoogle Scholar
  14. 14.
    T. Elewa, F. Balestra, S. Cristoloveanu, I. M. Hafez, J. P. Colinge, A. J. Auberton-Hervé, and J. R. Davis, Performance and physical mechanisms in SIMOX MOS transistors operated at very low temperature, IEEE Trans. Electron Dev., ED-37, p. 1007, 1990.CrossRefGoogle Scholar
  15. 15.
    G. Groseneken, J. P. Colinge, H. E. Maes, J. C. Alderman, and S. Holt, IEEE Electron Devices Lett., EDL-11, p. 329, 1990.CrossRefGoogle Scholar
  16. 16.
    J. Tihanyi and H. Schloterrer, Influence of the floating substrate potential on the characteristics of EFSI MOS transistor, Solid-St. Electron., 18, p. 305, 1975.CrossRefGoogle Scholar
  17. 17.
    F. Balestra, L. Audaire, and C. Lucas, Influence of substrate freeze-out on the characteristics of MOS transistors at very low temperatures, Solid-St. Electronics, 30, p. 321, 1987.CrossRefGoogle Scholar
  18. 18.
    J. P. Colinge, Reduction of kink effect in thin film SOI MOSFETs, IEEE Electron Dev. Lett., EDL-9, p. 97, 1988.CrossRefGoogle Scholar
  19. 19.
    I. M. Hafez, G. Ghibaudo, and F. Balestra, Analysis of the kink effect in MOS transistors, IEEE Trans. Electron Dev., ED-37, p. 818, 1990.CrossRefGoogle Scholar
  20. 20.
    C. E. D. Chen, M. Matloubian, R. Sundaresan, B. Y. Mao, C. C. Wei, and G. P. Pollack, Single-transistor latch in SOI MOSFET’s, IEEE Electron Dev. Lett., EDL-9, p. 636, 1988.CrossRefGoogle Scholar
  21. 21.
    M. Yoshimi, M. Takahashi, T. Wada, K. Kato, S. Kambayashi, M. Kemmoshi, and K. Natori, Analysis of the drain breakdown mechanism in ultra-thin-film SOI MOSFET’s, IEEE Trans. Electron Dev., ED-37, p. 2015, 1990.CrossRefGoogle Scholar
  22. 22.
    J. Y. Choi and J. G. Fossum, Analysis and control of floating body effects in fully depleted SOI MOSFET’s, IEEE Trans. Electron Dev., ED-38, p. 1384, 1991.CrossRefGoogle Scholar
  23. 23.
    J. Gautier and A. J. Auberton-Hervé, A latch phenomenon in buried N-body SOI NMOSFET’s, IEEE Electron Dev. Lett., EDL-12, p. 372, 1991.CrossRefGoogle Scholar
  24. 24.
    F. Balestra, J. Jomaah, G. Ghibaudo, O. Faynot, A. J. Auberton-Hervé, and B. Giffard, Analysis of the latch and breakdown phenomena in N and P channel thin film SOI MOSFET’s as a function of temperature, IEEE Trans. Electron Dev., ED-41, p. 109, 1994.CrossRefGoogle Scholar
  25. 25.
    S.-H. Renn, C. Raynaud, F. Balestra, Floating body and hot carrier effects in ultra-thin film SOI MOSFETs, Proc. WOLTE-2, in J. Phy. IV, Coll. 3, Supplément au J. de Phys. III, Vol. 6, p. C3–49, 1996.Google Scholar
  26. 26.
    J. Jomaah, G. Ghibaudo, and F. Balestra, Temperature dependence of gate-induced-drain-leakage (GIDL) current in thin-film SOI MOSFETs, The Electrochemical Society Proceedings Volume 95–9, 1995, p. 260.Google Scholar
  27. 27.
    K. Rais, F. Balestra, and G. Ghibaudo, Temperature dependence of gate induced drain leakage current in silicon CMOS devices, Electronics Letters, 30, p. 32, 1994.CrossRefGoogle Scholar
  28. 28.
    J. Chen, F. Assaderaghi, P. K. Ko, and C. Hu, The enhancement of Gate-Induced-Drain-Leakage (GIDL) current in short-channel SOI MOSFET and its application in measuring lateral bipolar current gain β, IEEE Electron Dev. Lett., EDL-13, p. 572, 1992.CrossRefGoogle Scholar
  29. 29.
    T. Ishijama and Y. Omura, Enhancement and suppression of band-to-band tunneling current in ultra-thin nMOSFETs/SIMOX: Influence of superficial Si layer thickness and it’s future prospect, Proc. SSDM’96, p. 314, 1996.Google Scholar
  30. 30.
    L. J. McDaid, S. Hall, P. H. Mellor, and W. Eccleston, Physical origin of negative differential resistance in SOI transistors, Electronics Letters, 25, p. 827, 1989.CrossRefGoogle Scholar
  31. 31.
    J. Jomaah, E. Rauly, G. Ghibaudo, F. Balestra, A thorough analysis of self-heating effects for SOI MOSFETs on SIMOX and UNIBOND substrates, Proc. WOLTE-3, in J. Phy. IV, France 8, p. 3–17, 1998.Google Scholar
  32. 32.
    L. T. Su, K. E. Goodson, D. A. Antoniadis, M. I. Flik, and J. E. Chung, Measurement and modeling of self-heating effects in SOI NMOSFETs, IEDM Tech. Dig., 1992, p. 357.Google Scholar
  33. 33.
    J. Jomaah, G. Ghibaudo, F. Balestra, Analysis and modelling of self-heating effects in thin-film SOI MOSFETs as a function of temperature. Solid-State Electronics, 38, p. 615, 1995.CrossRefGoogle Scholar
  34. 34.
    K. Kato and K. Taniguchi, Numerical Analysis of switching characteristics in SOI MOSFETs, IEEE Trans. Electron Devices, 33, p. 133, 1986.CrossRefGoogle Scholar
  35. 35.
    H. Hazama, M. Yoshimi, M. Takahashi, S. Kambayashi, and H. Tango, Suppression of drain current overshoot in SOI-MOSFETs using ultrathin SOI substrates, Electronics Lett., 24, p. 1266, 1988.CrossRefGoogle Scholar
  36. 36.
    J. Gautier, K. A. Jenkins, and J. Y.-C. Sun, Body charge related transient effects in floating body SOI NMOSFETs, IEDM Tech. Dig., p. 623, 1995.Google Scholar
  37. 37.
    E. Rauly, O. Potavin, F. Balestra, C. Raynaud, On the subthreshold swing and short channel effects in single and double gate deep submicron SOI MOSFETs, Solid-State Electronics, vol. 43, p. 2033, 1999.CrossRefGoogle Scholar
  38. 38.
    F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, Double-gate silicon-on-insulator transistor with volume inversion: a new device with greatly enhanced performance, IEEE Electron Dev. Lett., EDL-8, p. 410, 1987.CrossRefGoogle Scholar
  39. 39.
    M. Koyanagi, T. Matsumoto, T. Shimatani, F. Balestra, Y. Hiruma, M. Okabe, and Y. Inoue, Photon emission from SOI MOSFET with body terminal, IEDM Tech. Dig., 1994, p. 944.Google Scholar
  40. 40.
    Y. Omura, An improved analytical solution of energy balance equation for short-channel SOI MOSFET’s and transverse-field-induced carrier heating, IEEE Trans. Electron Dev., ED-42, p. 301, 1995.CrossRefGoogle Scholar
  41. 41.
    S. H. Renn, E. Rauly, J. L. Pelloie, F. Balestra, Impact of floating-body-induced parasitic bipolar transistor on hot-carrier effects in 0.1μm N-channel SOI MOSFETs, ECS Meeting, Symposium on low temperature electronics and high temperature superconductivity, Montreal, Proc. p. 199, Mai 1997.Google Scholar
  42. 42.
    S.-H. Renn, C. Raynaud, F. Balestra, Temperature dependence of hot carrier effects in 0.2μm N-and P-channel fully depleted Unibond MOSFETs, Proc. WOLTE-3, in J. Phy. IV, France 8, p. 3–13, 1998.Google Scholar
  43. 43.
    S. H. Renn, C. Raynaud, J. L. Pelloie and F. Balestra, “A Thorough Investigation of the Degradation Induced by Hot-Carrier Injection in Deep Submicron N-and P-Channel Partially-and Fully-Depleted Unibond and SIMOX MOSFETs”, IEEE Trans. Electron Devices, 45, p. 2146, 1998.CrossRefGoogle Scholar
  44. 44.
    Y. Nakajima and Y. Omura, Electron mobility in nMOSFETs/SIMOX with 2-nm-thick silicon layer, Proc. Int. IEEE SOI Conference, p. 11, 1996.Google Scholar
  45. 45.
    Y. Omura, S. Horiguchi, M. Tabe, and K. Kishi, Quantum-mechanical effects on the threshold voltage of ultrathin-SOI nMOSFET’s, IEEE Electron Dev. Lett., EDL-14, p. 569, 1993.CrossRefGoogle Scholar
  46. 46.
    Y. Omura and K. Izumi, Quantum mechanical influences on short-channel effects in ultra-thin MOSFET/SIMOX devices, IEEE Electron Device Lett., EDL-17, p. 300, 1996.CrossRefGoogle Scholar
  47. 47.
    K. Murase, Y. Takahashi, Y. Nakajima, H. Namatsu, M. Nagase, K. Kurihara, K. Iwadate, S. Horiguchi, M. Tabe, and K. Izumi, Transport properties of silicon nanostructures fabricated on SIMOX substrates, Microelectronics Engineering, p. 399, 1995.Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 2001

Authors and Affiliations

  • Francis Balestra
    • 1
  • Gérard Ghibaudo
    • 1
  1. 1.Laboratoire de Physique des Composants à SemiconducteursUMR CNRS, ENSERG/INPGGrenobleFrance

Personalised recommendations