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Lambda-Block Analysis of VHDL for Design Reuse

  • William Fornaciari
  • Salvatore Minonne
  • Fabio Salice
  • Massimo Vincenzi
Chapter

Abstract

The chapter presents a methodology to be used for both design and analysis of digital systems described by using VHDL. The developed CAD environment allows the designer to inspect the code of existing systems in order to extract candidate functionality suitable for reuse as well as to evaluate the quality of VHDL in a reuse perspective. The proposed methodology has been validated by considering small industrial benchmarks and by redesigning an industrial core cell, a PC-Card interface, used in commercial devices.

Keywords

Design Reuse VHDL Code Electronic Design Automation Silicon Capability Manpower Distribution 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media Dordrecht 2001

Authors and Affiliations

  • William Fornaciari
    • 1
  • Salvatore Minonne
    • 1
  • Fabio Salice
    • 1
  • Massimo Vincenzi
    • 1
  1. 1.Dipartimento di Elettronica e InformazionePolitecnico di MilanoMilanoItaly

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