A Method for Interface Customization of Soft IP Cores
In this chapter, we present an interface customization technique suitable for Soft IP cores, which are to be implemented as synthesizable VHDL models. By exploiting the features of VHDL+, an extension to VHDL, we separate the specifications of the IP functional behavior and IP interface protocols into two distinct IP design units. Interface customization is done through specification of system specific IP interface communication protocols, followed by an IP interface generation at signal level with our tool MODIS.
KeywordsInterface Specification Interface Signal VHDL Code Maximum Clock Frequency Module Port
Unable to display preview. Download preview PDF.