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High-Speed, Analyzable Simulators

  • David Greve
  • Matthew Wilding
  • David Hardin
Part of the Advances in Formal Methods book series (ADFM, volume 4)

Abstract

High-speed simulation models are routinely developed during the design of complex hardware systems in order to predict performance, detect design flaws, and allow hardware/software co-design. Writing such an executable model in ACL2 brings the additional benefit of formal analysis; however, much care is required to construct an ACL2 model that is both fast and analyzable. In this chapter, we develop techniques for the construction of high-speed formally analyzable simulators in ACL2, and demonstrate their utility on a simple processor model.

Keywords

Recursive Function Garbage Collection Program Counter Clock Function Type Declaration 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 2000

Authors and Affiliations

  • David Greve
    • 1
  • Matthew Wilding
    • 1
  • David Hardin
    • 2
  1. 1.Rockwell Collins Advanced Technology CenterCedar RapidsUSA
  2. 2.Ajile Systems, Inc.OakdaleUSA

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