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Using Macros to Mimic VHDL

  • Dominique Borrione
  • Philippe Georgelin
  • Vanderlei Rodrigues
Part of the Advances in Formal Methods book series (ADFM, volume 4)

Abstract

The purpose of this project is to define in ACL2 the semantics of a small synthesizable behavioral subset of VHDL. The intention is to preserve, as much as possible, the syntactic flavor of VHDL, and to facilitate the verification of a circuit design by symbolic simulation and theorem proving techniques. The definition is written with macros, which recognize VHDL keywords and construct semantic functions and some basic theorems, for each main statement of the language. This project introduces type definitions, signal and variable declarations, and simple processes. Declarations define the initial state of a system. Statements and processes are functions that map states to (next) states. The systematic use of macros helps by introducing infix notation, employing keywords that strongly resemble corresponding VHDL syntax.

Keywords

Clock Cycle State Element Semantic Function Symbolic Expression Simulation Cycle 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 2000

Authors and Affiliations

  • Dominique Borrione
    • 1
  • Philippe Georgelin
    • 1
  • Vanderlei Rodrigues
    • 1
    • 2
  1. 1.TIMA-UJFGrenobleFrance
  2. 2.II-UFRGSBrazil

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