Instruction Scheduling for Clustered VLIW Processors

  • Rainer Leupers


This chapter presents a code optimization technique for a special class of processor data paths, which we call clustered VLIW. Here, a cluster denotes a piece of the data path with functional units (FUs) and a local register file. Such a data path architecture is frequently found in multimedia processors and ASIPs. We will focus on the problem of instruction scheduling. Fig. 4.1 shows how this phase relates to the overall compilation flow.


Critical Path Control Step List Schedule Schedule Length Instruction Schedule 


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Copyright information

© Springer Science+Business Media Dordrecht 2000

Authors and Affiliations

  • Rainer Leupers
    • 1
  1. 1.University of DortmundGermany

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