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Deriving Signal Transition Graphs from Behavioral Verilog HDL

  • Ivan Blunno
  • Luciano Lavagno
Chapter

Abstract

We propose a design flow for asynchronous circuits that closely mimics the standard synchronous ASIC design flow. Key elements of the flow are HDL-based specification, logic synthesis and physical design. In this work we present a proposal for using a standard HDL, Verilog, to specify an asynchronous control circuit at the behavioral level. This pecification is automatically translated in a Signal Transition Graph, that can then be automatically synthesized by existing tools.

Advantages of this methodology include rapid path to implementation, re-use of simulation patterns between pre- and post-synthesis steps, and designer familiarity with the specification language.

Keywords

asynchronous control circuits HDL Petri nets Signal Transition Graphs Verilog VHDL 

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Copyright information

© Springer Science+Business Media Dordrecht 2000

Authors and Affiliations

  • Ivan Blunno
    • 1
  • Luciano Lavagno
    • 2
  1. 1.Politecnico di TorinoTorinoItaly
  2. 2.Universitá di UdineUdineItaly

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