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Modeling a Memory Subsystem with Petri Nets: A Case Study

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Book cover Hardware Design and Petri Nets

Abstract

Memory subsystems often turn out to be the main performance bottleneck in current computer systems. Nevertheless, the architectural features of common RAM chips are not utilized to their limits. Therefore, a complex Petri Net model of a memory subsystem was developed and investigated to explore possible improvements. This chapter reports the results of a case study in which widely used synchronous RAMs were examined. It demonstrates how impressive throughput increases can be obtained by an enhanced memory controller scheme that could even make second level caches redundant in cost or power dissipation critical systems.

Furthermore, using colored time Petri nets leads to a descriptive view of the memory subsystem because a Petri Net model combines data and control flow as well as structural information in a natural way. The case study finally underpins the advantages of this approach.

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Author information

Authors and Affiliations

  1. Computer Engineering and Networks Laboratory (TIK), Swiss Federal Institute of Technology (ETH) Zurich, CH-8092, Zürich, Switzerland

    Matthias Gries

Authors
  1. Matthias Gries
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Editor information

Editors and Affiliations

  1. University of Newcastle upon Tyne, UK

    Alex Yakovlev

  2. Universidade Nova de Lisboa, Portugal

    Luis Gomes

  3. Universitá di Udine, Italy

    Luciano Lavagno

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© 2000 Springer Science+Business Media Dordrecht

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Gries, M. (2000). Modeling a Memory Subsystem with Petri Nets: A Case Study. In: Yakovlev, A., Gomes, L., Lavagno, L. (eds) Hardware Design and Petri Nets. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-3143-9_15

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  • DOI: https://doi.org/10.1007/978-1-4757-3143-9_15

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-4969-1

  • Online ISBN: 978-1-4757-3143-9

  • eBook Packages: Springer Book Archive

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