Analog Circuit Design pp 191-225 | Cite as

# MOS Transistor Modeling Issues for RF Circuit Design

## Abstract

This paper presents the basis of the modeling of the MOS transistor for circuit simulation at radio-frequency (RF). A physical equivalent circuit that can easily be implemented as a Spice subcircuit is first derived. In addition to the intrinsic device and the source and drain series resistance, the model also has a gate resistance, that is fundamental to correctly model the frequency and noise behavior. The subcircuit also includes a substrate network that accounts for the signal coupling occurring at HF from the drain to the source and the bulk. It is shown that the latter mainly affects the output admittance *y* _{22}. The bias and geometry dependence of all the subcircuit components, leading to a scalable model, are then discussed with emphasis on the substrate resistances. Analytical expressions of the Y-parameters, the transit frequency and the maximum oscillation frequency are established and compared to measurements made on a 0.25 p m CMOS process. The Y-parameters and transit frequency simulated with this scalable model versus frequency, geometry and bias are in good agreement with measured data The non-quasi-static effects and their practical implementation in the Spice subcircuit are then briefly discussed. Finally, a new thermal noise model is introduced and compared to noise models available in BSIM3v3. The parameters used to characterize the noise at HF are then presented and the scalable model is favorably compared to measurements made on the same devices.

## Keywords

Thermal Noise Strong Inversion Intrinsic Capacitance Velocity Saturation Bias Dependence## Preview

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