Abstract
In the last several years, there has been increasing demand by consumers and small businesses for higher speed connectivity to the Internet. ADSL promises to fulfill the demand for faster data rates. However, in order to achieve the highest data rates for a given line, careful consideration must be given to the analog front end design such that it does not become the limiting factor. Based on recent publications, the fundamental techniques for building analog front ends are explored. Possibilities for future advancements in analog front ends are addressed in the conclusion.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Chang, Z.Y., et al. “A CMOS Analog Front-End Circuit for an FDMBased ADSL System,” IEEE J. Solid-State Circuits, vol. 30, no. 12, pp. 1449–1456, Dec. 1995.
Durham, A.M. and Redham-White, W., “Integrated continuous-time balanced filter for 16-bit DSP interfaces,” IEEE J. Solid-State Circuits, vol. 28, pp. 835–839, Jul. 1993.
Yin, G. and Sansen, W., “A high frequency and high resolution fourth order Sigma Delta A/D converter in BiCMOS technology,” IEEE J. Solid-State Circuits, vol. 29, pp 857–865, Aug. 1994.
Cabler, C.D, “Fourth-Order Cascaded Sigma-Delta Modulator”, US Patent 5414–424.
Ritoniemi, T., et al., “The design of stable high order 1-bit sigma-delta modulators,” Proc. IEEE ISCAS, 1990, pp. 3267–3270.
Lee, W.L., and Sodini, C.G., “A topology for high order interpolative coders,” Proc. IEEE ICCAS, 1987, pp. 459–462.
Analog Devices, Inc. “AD6437, Analog Front End for ADSL”.
Lanford, D.S, et al., “A BiCMOS Analog Front-End Circuit for an FDM-Based ADSL System,” IEEE J. Solid State Circuits, vol. 33, no. 9, Sep. 1998, pp. 1383–1393.
Tesch, B.J. and Garcia, J.C., “A low glitch 14 bit 100Mhz D/A converter,” IEEE J. Solid State Circuits, vol. 32, Sep. 1997, pp. 1465–1469.
Cornil, J.P., et al., “CODEC for Echo-Cancelling, Full-Rate ADSL Modems,” ISSCC Digest of Technical Papers, San Francisco, CA, Feb. 1999, pp. 242–243.
Conroy, C., et al., “A CMOS Analog Front-End IC for DMT ADSL,” ISSCC Digest of Technical Papers, San Francisco, CA, Feb. 1999, pp. 240–241.
Hester, R., et al., “CODEC for Echo-Canceling, Full-Rate ADSL Modems,” ISSCC Digest of Technical Papers, San Francisco, CA, Feb. 1999, pp. 242–243.
Lewis, S., et al., “A 10-b 20Msample/s Analog-to-Digital Converter,” IEEE J. S.lid State Circuits, vol. 27, No. 3, March, 1992, pp. 351–358.
Baird, R.T. and Fiez, T., “Linearity Enhancement of Mutability SD A/D and D/A Converters Using DWA,” IEEE Transactions on Circuits and Systems, Vol. 42, No. 12, Dec. 1995, pp. 753–762.
van der Zwan, E.J., et al., “A 13mW 500kHz Data Acquisition IC with a 4.5 Digit DC and 0.02% Accurate True-RMS Extraction,”, ISSCC Digest of Technical Papers, San Francisco, CA, Feb. 1999, pp. 398–399.
Moyal, M. et al., “A 25kft 768kb/s CMOS Transceiver for Multiple Bit-Rate DSL”, ISSCC Digest of Technical Papers, San Francisco, CA, Feb. 1999, pp. 398–399.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1999 Springer Science+Business Media Dordrecht
About this chapter
Cite this chapter
Cabler, C.D. (1999). Survey of the State of the Art Analog Front End Circuit Techniques for ADSL. In: Sansen, W., Huijsing, J., van de Plassche, R. (eds) Analog Circuit Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-3047-0_5
Download citation
DOI: https://doi.org/10.1007/978-1-4757-3047-0_5
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-5101-4
Online ISBN: 978-1-4757-3047-0
eBook Packages: Springer Book Archive