The MOS Transistor at High Frequencies
Modern designs of telecommunications transceivers employ different technologies (GaAs, BiCMOS/bipolar, CMOS) depending on the frequency of operation of each stage. Evidently, this practice dramatically increases the system cost but it is a one way solution in many cases. However, at the low end of the frequency band (800 to 2400 MHz), it is now feasible to implement the complete system using Si-based technologies. This fact, drastically reduces the manufacturing cost and increases the integration level — a very desirable feature especially in mobile communication systems. Further cost reductions are possible if it becomes feasible to design and implement the complete transceiver in a pure CMOS technology which is the less costly solution and simultaneously, exhibits the highest level of integration. This solution is investigated in research projects from the Academia but the Industry still remains reluctant in adopting it mainly due to the fact that the MOS transistor exhibits poorer performance than its bipolar counterpart, especially at high frequencies of operation.
KeywordsDrain Current CMOS Technology nMOS Transistor pMOS Transistor Strong Inversion
Unable to display preview. Download preview PDF.
- R.H. Yan, K.F. Lee, D.Y. Jeon, Y.O. Kim,“High performance 0.1 micron room temperature Si MOSFETS,” in Digest of Technical Papers, 1992 Symposium on VLSI Technology, Seattle, WA, 2–4 June 1992, pp. 763–766.Google Scholar
- C. Jian, S. Parke, J. King, F. Assaderaghi, et al., “A high speed SOI technology with 12ps/18ps gate delay operating at 1.5V,” in Proceedings of IEEE Electron Devices Meeting, San Francisco, CA, 13–16 Dec. 1992.Google Scholar
- Y.P. Tsividis, Operation and Modeling at the MOS Transistor, Mc GrawHill, 1987.Google Scholar
- Y.P. Tsividis, Mixed Analog-Digital VLSI Devices and Technology, Mc Graw-Hill, 1995.Google Scholar
- P.R. Gray and R.G. Meyer, Analysis and Design of Analog Integrated Circuits, John Wiley, 1992.Google Scholar
- A.S. Machado Ed., “Low Power HF Microelectronics,” IEE Circuits and Systems, 1996.Google Scholar
- D.K. Shaeffer and T.H. Lee, “A 1.5V, 1.5 GHz CMOS Low Noise Amplifier,” IEEE JSSC, vol. 32, no. 5, pp. 745–759, May 1997.Google Scholar
- R.P. Jindal, “Noise associated with distributed resistance of MOSFET gate structures in integrated circuits,” IEEE Trans. Electron Devices, vol. ED-31, pp. 1505–1509, Oct. 1984.Google Scholar
- A. van der Ziel, Noise in Solid State Devices and Circuits, Wiley, New York, 1986.Google Scholar
- Q. Huang, F. Piazza, P. Orsatti, and T. Ohguro, “The Impact of Scaling Down to Deep Submicron on CMOS RF Circuits,” in Proceedings of the 23rd ESSCIRC Conference, Southampton UK, 16–18 September 1997, pp. 132–135.Google Scholar
- Y.P. Tsividis and K. Suyama, “MOSFET Modeling for Analog Circuit CAD: Problems and Prospects,” IEEE JSSC, vol. 29, no. 3, pp. 210–216, March 1994.Google Scholar