Advertisement

Digital design for low switching noise

  • Xavier Aragonès
  • José Luis González
  • Antonio Rubio
Chapter

Abstract

This chapter looks at the relationship between the digital design process and the switching noise generated by the circuits finally obtained. This analysis is performed on all levels: abstract, structural, logic, and circuit. High-level synthesis and logic synthesis processes are examined and some low switching noise design rules are derived. Switching noise in output drivers is tackled by proper design techniques that are summarized at the end of the chapter

Keywords

Very Large Scale Integration Dynamic Logic Noise Margin High Level Design Logic Alternative 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    Peter J. Ashenden. (1996). The Designer Guide to VHDL. 1st edition. San Francisco: Morgan Kaufmann Publishers.Google Scholar
  2. [2]
    D.E. Thomas, P.R. Moorby. (1991). The Verilog Hardware Description Language. Boston: Kluwer Academic Publishers.CrossRefGoogle Scholar
  3. [3]
    Hamburg VHDL Archive, Available in the WWW, URL <http://tech-www.informatik.unihamburg.de/vhdl/vhdl.html>, University of Hamburg.
  4. [4]
    Synergy Synthesis Tools, Cadence Opus DFWII release 9502.Google Scholar
  5. [5]
    D.E. Thomas, P.R. Moorby (1991) The Verilog Hardware Description Language. Massachusetts: Kluwer Academic Publishers.CrossRefGoogle Scholar
  6. [6]
    Pierre G. Paulin, Hohn P. Knight, ‘Force-Directed Scheduling for the Behavioral Synthesis of ASIC’s’, IEEE Tr. on Computer-Aided Design, Vol. 8, No. 6, June 1989, pp. 661–679.CrossRefGoogle Scholar
  7. [7]
    Sabine März. ‘High-Level Synthesis’ in The Synthesis Approach to Digital System Design, Petra Michel, Ultich Lauter, and Peter Duzy, Ed. (1992). Massachusetts: Kluwer Academic Publishers.Google Scholar
  8. [8]
    Daniel Gajski, Nikil Dutt, Allen Wu, and Steve Lin. (1992). High-Level Synthesis: Introduction to Chip and System Design. Massachusetts: Kluwer Academic Publishers.Google Scholar
  9. [9]
    Luca Benini, and Giovani De Micheli, ‘State Assignment for Low Power Dissipation’, IEEE J. Solid-State Circuits, Vol. 30, No. 3, March 1995, pp. 258–267.CrossRefGoogle Scholar
  10. [10]
    Luca Benini, and Giovani De Micheli, ‘Automatic Synthesis of Low-Power Gated-Clock Finite-State Machines’, IEEE Tr. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, No. 6, June 1996, pp. 630–643.CrossRefGoogle Scholar
  11. [11]
    Manfred Koegst, Günter Franke, Steffen Rülke, and Klaus Feske, ‘A Strategy for Low Power FSM-Design by Reducing Switching Activity’, Proc. of 7th Int. Workshop PATMOS’97, Lauvainla Neuve, Belgium, 8–10 September 1997, pp. 119–128.Google Scholar
  12. [12]
    Neil H.E. Weste, Kamran Eshraghian, Principles of CMOS VLSI Design. A systems perspective. 2d. Edition (1994). Massachusetts: Addison-Wesley Publishing Company.Google Scholar
  13. [13]
    Richard X.Gu, Khaled M. Sharaf, Mohamed I. Elmasry. High-Performance Digital VLSI Circuit Design. 1996. Massachusetts: Kluwer Academic Publishers.Google Scholar
  14. [14]
    K. Yano, et al., ‘3.8-ns CMOS 16x 16-b Multiplier Using Complementary Pass-Transistor Logic’, IEEE J. Solid-State Circuits, Vol. SC-25, April 1990, pp. 388–395.CrossRefGoogle Scholar
  15. [15]
    M. Suzuki, et al., ‘A 1.5-ns 32-b CMOS ALU Double Pass-Transistor Logic’, IEEE J. Solid-State Circuits, Vol. SC-28, Nov. 1993, pp. 1145–1151.CrossRefGoogle Scholar
  16. [16]
    Patrik Larsson, and Christer Svensson, ‘Noise in Digital Dynamic CMOS Circuits’, IEEE J. Solid-State Circuits, Vol. 29, No. 6, June 1994, pp. 655–662.CrossRefGoogle Scholar
  17. [17]
    R.H. Krambeck, Charles M. Lee, and Hung-Fai Stephen Law, ‘High-Speed Compact Circuits with CMOS’, IEEE J. Solid-State Circuits, Vol. SC-17, No. 3, June 1981, pp. 614–619.CrossRefGoogle Scholar
  18. [18]
    V. Friedman and S. Liu, ‘Dynamic Logic CMOS Circuits’, IEEE J. Solid-State Circuits, Vol. SC-19, April 1984, pp. 263–266.CrossRefGoogle Scholar
  19. [19]
    C.M. Lee, and E. W. Szeto, ‘Zipper CMOS’, IEEE Circuits & Devices Mag., May 1986, pp. 10–16.Google Scholar
  20. [20]
    Kan M. Chu, and David L. Pulfrey, ‘A comparison of CMOS Circuit Techniques: Differential Cascode Voltage Switch Logic Versus Conventional Logic’, IEEE J. Solid-State Circuits, Vol. SC-22, No. 4, August 1987, pp. 528–532.CrossRefGoogle Scholar
  21. [21]
    Leo C.M.G. Pfennings, Wim G.J. Mol, Joseph J.J. Bastiaens, and Jan M.F. Van Dijk, ‘Differential Split-Level CMOS Logic for Subnanosecond Speeds’, IEEE J. Solid-State Circuits, Vol. SC-20, No. 5, October 1985, pp. 1050–1055.CrossRefGoogle Scholar
  22. [22]
    Yasoji Susuki, Kaicho Odagawa, and Toshio Abe, ‘Clocked CMOS Calculator Circuitry’, IEEE J. Solid-State Circuits, Vol. SC-8, No. 6, Dec. 1973, pp. 462–469.CrossRefGoogle Scholar
  23. [23]
    Nelson F. Goncalves, Hugo J. De Man, ‘NORA: A Recefree Dynamic CMOS Technique for Pipelined Logic Structures’, IEEE J. Solid-State Circuits, Vol. SC-18, No.3, June 1983, pp. 261–266.CrossRefGoogle Scholar
  24. [24]
    Jiren Yuan and Christer Svensson, ‘High-Speed CMOS Circuit Technique’, IEEE J. Solid-State Circuits, Vol. 24, No. 1, February 1989, pp. 62–70.CrossRefGoogle Scholar
  25. [25]
    Timothy A. Grotjohn, and Bernd Hoeflinger, ‘Sample-Set Differential Logic (SSDL) for Complex High-Speed VLSI’, IEEE J. Solid-State Circuits, Vol. SC-21, No. 2, April 1986, pp. 367–369.CrossRefGoogle Scholar
  26. [26]
    Kan M. Chu, and David L. Pulfrey, ‘Design Procedures for Differential Cascade Voltage Switch Circuits’, IEEE J. Solid-State Circuits, Vol. SC-21, No. 6, December 1986, pp. 1082–1087.CrossRefGoogle Scholar
  27. [27]
    Jordi Cortadella, ‘Mapping BDD’s Into DCVSL Gates (or Switch-Level Synthesis)’, Research report of the Computer Architecture Dep’t, Universitat Politècnica de Catalunya, August 1992.Google Scholar
  28. [28]
    Shih-Lien L. Lu, and Milos D. Ercegovac, ‘Evaluation of Two-Summand Adders Implemented in ECDL CMOS Differential Logic’, IEEE J. Solid-State Circuits, Vol. 26, No. 8, August 1991, pp. 1152–1160.CrossRefGoogle Scholar
  29. [29]
    Wei-han Lien, and Wayne P. Burleson, Wave-Domino Logic: Theory and Application’, IEEE Tr. on Circuits and Systems—II, Vol. 42, No. 2, February 1995, pp. 78–91.CrossRefGoogle Scholar
  30. [30]
    C.H. Lau, D. Renshaw, and J. Mayor, ‘A Self-Timed Wavefront Array Multiplier’, Proc. of 1989 Int. Symp. on Circuits and Systems (ISCAS’89), pp. 138–141.Google Scholar
  31. [31]
    Vitit Kantaburata, and Andreas G. Andreou, ‘A State Assignment Approach to Asynchronous CMOS Circuit Design’, IEEE Tr. on Computers, Vol. 43, No. 4, April 1994, pp. 460–469.CrossRefGoogle Scholar
  32. [32]
    Bob Mammano, ‘Fuelling the Megaprocessors — Empowering Dynamic Energy Management’, —.Google Scholar
  33. [33]
    Rich Evans, and Michael Tsuk, ‘Modelling and Measurement of High-Performance Computer Power Distribution System’, IEEE Tr. on Components, Packaging, and Manufacturing Tech.— Part B, Vol. 17, No. 4, November 1994, pp. 467–471.CrossRefGoogle Scholar
  34. [34]
    VRM 9.1 DC-DC Converter Design Guidelines. Intel Application Notes, Order Number 243408–001. May 1997.Google Scholar
  35. [35]
    Anantha P. Chandrakasan, Samuel Sheng, and Robert W. Brodersen, ‘Low-Power CMOS Digital Design’, IEEE J. Solid-State Circuits, Vol. 27, No. 4, April 1992, pp. 473–484.CrossRefGoogle Scholar
  36. [36]
    Anantha P. Chandrakasan, Miodrag Potkonjak, Renu Mehra, Jan Rabaey, and Robert W. Brodersen, ‘Optimising Power Using Transformations’, IEEE Tr. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 14, No. 1, January 1995, pp. 12–31.CrossRefGoogle Scholar
  37. [37]
    Jan M. Rabaey, and Massoud Pedram, editors. Low Power Design Methodologies, 1996, Massachusetts: Kluwer Academic Publishers.Google Scholar
  38. [38]
    Vasily G. Moshnyaga and Keikichi Tamaru, ‘A Comparative Study of Switching Activity Reduction Techniques for Design of Low-Power Multipliers’, Proc. of 1995 IEEE Int. Symp. Circuits and Systems: ISCAS’95, pp. 1560–1563.Google Scholar
  39. [39]
    Anantha P. Chandrakasan, and Robert Brodersen. Low Power Digital CMOS Design. 1995. Massachusetts: Kluwer Academic Publishers.CrossRefGoogle Scholar
  40. [40]
    P. Girard, C. Landrault, S. Pravossoudovitch, and D. Severac, ‘Technique for Reducing Power Consumption in CMOS Circuits’, Electronics Letters, Vol. 33, No. 6, March 1997, pp. 485–486.CrossRefGoogle Scholar
  41. [41]
    R. Iris Bahar, Fabio Somenzi, ‘Boolean Techniques for Low Power Driven Re-Synthesis’, Proc. of IEEE ICAD Conf, 1995, pp. 428–432.Google Scholar
  42. [42]
    G. Theodoridis, S. Theoharis, D. Soudris, O. Koufopavlou, and C. Goutis, ‘A Novel Approach for Reducing the Switching Activity in Two-Level Logic Circuits’, Proc. of ICECS, 1996, pp. 840–843.Google Scholar
  43. [43]
    E.E. Davidson, ‘Electrical Design of a High Speed Computer Package’, IBM J. Res. Develop., Vol. 26, No. 3, May 1982, pp. 349–361.CrossRefGoogle Scholar
  44. [44]
    George A. Katopis, ‘Delta-I Noise Specification for a High-Performance Computing Machine’, Proceedings of the IEEE, Vol. 73, No. 9, September 1985, pp. 1405–1415.CrossRefGoogle Scholar
  45. [45]
    Arun Vaidyanath, Bigir Thoroddsen, and J.L. Prince, ‘Effect of CMOS Driver Loading Conditions on Simultaneous Switching Noise’, IEEE Tr. on Components, Packaging, and Manufacturing Techn.-Part B, Vol. 17, No. 4, November 1994, pp. 480–485,CrossRefGoogle Scholar
  46. [46]
    Hung Chang Lin, and Loren W Linholm, ‘An Optimized Output Stage for MOS Integrated Circuits’, IEEE J. Solid-State Circuits, Vol. SC-10, No. 2, April 1975, pp. 106–109.CrossRefGoogle Scholar
  47. [47]
    Srivasa R. Vemuru, ‘Effects of Simultaneously Switching Noise on the Tapered Buffer Design’, IEEE Tr. on Very Large Scale Integration (VLSI) Systems, Vol. 5, No. 3, September de 1997, pp. 290–300.CrossRefGoogle Scholar
  48. [48]
    Yaochao Yang, and John R. Brews, ‘Design Trade-Offs for the Last Stage of an Unregulated, Long-Channel CMOS Off-Chip Driver with Simultaneous Switching Noise and Switching Time Considerations’, IEEE Tr. on Components, Packaging, and Manufacturing Techn.-Part B, Vol. 19, No. 3, August 1996, pp. 481–486.CrossRefGoogle Scholar
  49. [49]
    Yahochao Yang and John R. Brews, ‘Design for Velocity Saturated, Short-Channel CMOS Drivers with Simultaneous Switching Noise and Switching Time Considerations’, IEEE J. Solid-State Circuits, Vol. 31, No. 9, September 1996, pp. 1357–1360.CrossRefGoogle Scholar
  50. [50]
    Thaddeus J. Gabara, Wilhelm C. Fischer, John Harrington, and William W. Troutman, ‘Forming Damped LRC Parasitic Circuits in Simultaneously Switched CMOS Output Buffers’, IEEE J. Solid-State Circuits, Vol. 32, No. 3, March. 1997, pp. 407–418.CrossRefGoogle Scholar
  51. [51]
    R. Senthinathan, J.L. Prince, and S. Nimmagadda, ‘Noise Immunity Characteristics of CMOS Receivers and Effects of Skewing/Damping CMOS Driver Switching Waveform on the Simultaneous Switching Noise’, Microelectronics Journal, Vol 23, 1992, pp. 29–36.CrossRefGoogle Scholar
  52. [52]
    Karl L. Wang, Mark. D. Bader, Vince W. Soorholtz, Richard W. Mauntel, Horacio J. Mendez, Peter H. Voss, and Roger I. Kung, ‘A 21-ns 32Kx8 CMOS Static RAM with a Selectively Pumped p-Well Array’, IEEE J. Solid-State Circuits, Vol. SC-22, No. 5, October 1987, pp. 704–711.CrossRefGoogle Scholar
  53. [53]
    L. Alberston, S. Witaker and R. Merrell, ‘CMOS Output Buffer Waveshaping’, Proc. of 1st Great Lakes Symp. on VLSI, 1991, pp. 326–327.Google Scholar
  54. [54]
    R. Senthinathan, and J.L. Prince, ‘Application-Specific CMOS Output Driver CIrcuit Design Techniques to Reduce Simultaneous Switching Noise’, IEEE J. Solid-State Circuits, Vol. 28, No. 12, December 1993, pp. 1383–1388.CrossRefGoogle Scholar
  55. [55]
    C.S. Choy, M.H. Ku, and C.F. Chan, ‘A Low Power-Noise Output Driver with an Adaptative Characteristic Applicable to a Wide Range of Loading Conditions’, IEEE J. Solid-State Circuits, Vol. 32, No. 6, June 1997, pp. 913–917.CrossRefGoogle Scholar
  56. [56]
    Donald T. Wong, R. Dean Adams, Arup Bhattacharyya, James Covino, John A. Gabric, and George M. Lattimore, ‘An 11-ns 8k × 18 CMOS Static RAM with 0.5-μm Devices’, IEEE J. Solid-State Circuits, Vol. 23, No. 5, October 1988, pp. 1095–1103.CrossRefGoogle Scholar
  57. [57]
    K. Furutani, H. Miyamoto, Y. Morooka, M. Suwa, and H. Ozaki, ‘An Adjustable Output Driver with a Self-Recovering Vpp Generator for a 4M × 16 DRAM’, IEEE J. Solid-State Circuits, Vol. 29, No. 3, March 1994, pp. 308–310.CrossRefGoogle Scholar
  58. [58]
    Tomohisa Wada, Toshihiko Hirose, Hirofumi Shinohara, Yuji Kawai, Kojiro Yuzuriha, Yoshiho Kohono, and Shimpei Kayano, ‘A 34-ns 1-Mbit CMOS SRAM using triple Polysilicon’, IEEE J. Solid-State Circuits, Vol. SC-22, No. 5, October 1987, pp. 727–732.CrossRefGoogle Scholar
  59. [59]
    Ernestina Chiofi, Franco Maloberti, Gianmarco Marchesi, and Guido Torelli, ‘High-Speed, Low-Switching Noise CMOS Memory Data Output Buffer’, IEEE J. Solid-State Circuits, Vol. 29, No. 11, November 1994, pp. 1359–1365.CrossRefGoogle Scholar
  60. [60]
    Tomonori Sekiguchi, Masashi Horiguchi, Takeshi Sakata, Yoshinobu Nakagome, Shigeki Ueda, and Masakazu Aoki, ‘Low-Noise, High-Speed Data Transmission Using a Ringing-Canceling Output Buffer’, IEEE J. Solid-State Circuits, Vol.30, No. 12, December 1995, pp. 1569–1574.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 1999

Authors and Affiliations

  • Xavier Aragonès
    • 1
  • José Luis González
    • 1
  • Antonio Rubio
    • 1
  1. 1.Universitat Politècnica de Catalunya (UPC)Spain

Personalised recommendations