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Introduction

  • Xavier Aragonès
  • José Luis González
  • Antonio Rubio
Chapter

Abstract

Today’s VLSI electronic technology allows complex mixed-mode circuits to be integrated in a single silicon die, with high speed digital circuits fitted alongside high performance analog sections. Noise immunity has been one of the classical drawbacks of analog circuits as opposed to digital ones. In the last few years, the resolution demanded of such circuits has increased because of the need to process very low level signals and through the increasing quality demanded in audio or video communications. Analog circuit designers traditionally had to deal with noise sources related with devices, mainly thermal, shot and flicker (1/f) noise [I]. The trends in microelectronics are nevertheless heading towards integrating full systems in a single chip, including analog and digital parts. This fact makes device noise no longer the main source of noise affecting analog circuitry, this being instead the disturbances that digital circuitry induces over the analog part. The problem is made worse because of the increasing density of integration and the growing speed of digital circuits, which make the noise produced larger and larger.

Coupling problems have become a limiting factor in the performance of many advanced circuits. This has brought about a need for research in the field, in order to find the way all these effects are produced, and what can be done to avoid them. This book focuses on the analysis of coupling mechanisms, specifically noise coupled through the silicon substrate shared by analog and digital circuitry in a mixed-signal IC due to dV/dt as well as on the parasitic coupling through packaging due to dl/dt. This introductory chapter contains a review of the state of the art in microelectronics, to look at its evolution and thus understand the factors which lead to the aforementioned situation

Keywords

Digital Circuit VLSI Circuit Multichip Module Digital Circuitry Advanced Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    Low-Noise Wide-Band Amplifiers in Bipolar and CMOS Technologies, Z.Y. Chang, W. Sansen, Chapt. 2, Kluwer Academic Publishers, 1991.Google Scholar
  2. [2]
    Chenming Hu, “Future CMOS Scaling and Reliability”, Proceedings of the IEEE, vol. 81, no. 5, pp. 682–689, May 1993.CrossRefGoogle Scholar
  3. [3]
    CAD and Testing of ICs and Systems. Where are we going?, B. Courtois, TEV1A-CMP, France 1996.Google Scholar
  4. [4]
    R.H. Dennard, F.H. Gaensslen, H.N. Yu, V.L. Rideout, E. Bassous, A.R. LeBlanc, “Design of Ion-Implanted MOSFET’s with Very Small Physical Dimensions”, IEEE J. Solid-State Circuits, vol. 9, no. 5, pp. 256–267, October 1974.CrossRefGoogle Scholar
  5. [5]
    G.E. Moore, “Progress in Digital Integrated Electronics”, Proc. IEEE Int. Electron Devices Meeting, pp. 11–13, 1975.Google Scholar
  6. [6]
    G.E. Moore, “Lithography and the Future of Moore’s Law”, Optical/Laser Microlithography VIII: Proceedings of the SPIE, 2440, pp. 2–17, February 1995.Google Scholar
  7. [7]
    The National Technology Roadmap for Semiconductors, Semiconductor Industry Association, 1994, document available at: http://www.sematech.org/public/roadmap/index.htm.Google Scholar
  8. [8]
    Physical Architecture of VLSI Systems, R.J. Hannemann, A.D. Kraus, M. Precht, John Wiley & Sons, 1994.Google Scholar
  9. [9]
    E.T. Lewis, “An Analysis of Interconnect Line Capacitance and Coupling for VLSI Circuits”, Solid-State Electronics, vol. 27, nos. 8/9, pp. 741–749, 1984.CrossRefGoogle Scholar
  10. [10]
    S. Seki, H. Hasegawa, “Analysis of Crosstalk in Very High-Speed LSI/VLSI’s Using a Coupled Multiconductor MIS Microstrip Line Model”, IEEE Trans. Microwave Theory and Techniques, vol. 32, no. 12, pp. 1715–1720, December 1984.CrossRefGoogle Scholar
  11. [11]
    F. Moll, M. Roca, A. Rubio, “Measurement of Crosstalk-Induced Delay Errors in Integrated Circuits”, Electronics Utters, vol. 33, no. 19, pp. 1623–1624, September 1997.CrossRefGoogle Scholar
  12. [12]
    F. Moll, A. Rubio, “Spurious Signals in Digital CMOS VLSI Circuits, a Propagation Analysis”, IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 39, no. 10, pp. 749–752, October 1992.MATHCrossRefGoogle Scholar
  13. [13]
    T. Hameenanttila, J.D. Carothers, Donghui Li, “Fast Coupled Noise Estimation for Crosstalk Avoidance in the MCG Multichip Module Autorouter”, IEEE Trans. Very Large Scale Integration Systems, vol. 4, no. 3, pp. 356–368, September 1996.CrossRefGoogle Scholar
  14. [14]
    B.P. Brandt, B.A. Wooley, “A 50-MHz Multibit Sigma-Delta Modulator for 12-b 2-MHz A/D Conversion”, IEEE J. Solid-State Circuits, vol. 26, no. 12, pp. 1746–1756, December 1991.CrossRefGoogle Scholar
  15. [15]
    T. Tsuruda, M. Kobayashi, M. Tsukude, T. Yamagata, K. Arimoto, M. Yamada, “High-Speed/High Bandwidth Design Methodologies for On-Chip DRAM Core Multimedia System LSI’s”, IEEE J. Solid-State Circuits, vol. 32, no. 3, pp. 477–482, March 1997.CrossRefGoogle Scholar
  16. [16]
    E.A. Vittoz, “The Design of High-Performance Analog Circuits on Digital CMOS Chips”, IEEE J. Solid-State Circuits, vol. 20, no. 3, pp. 655–665, June 1985.CrossRefGoogle Scholar
  17. [17]
    D.K. Su, B.A. Wooley, “A CMOS Oversampling D/A Converter with a Current-Mode Semidigital Reconstruction Filter”, IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 1224–1233, December 1993.CrossRefGoogle Scholar
  18. [18]
    D.K. Su, M.J. Loinaz, B.A. Wooley, “Experimental Results and Modeling Techniques for Switching Noise in Mixed-Signal Integrated Circuits”, Proc. Symposium on VLSI Circuits, pp. 42–43, 1992.Google Scholar
  19. [19]
    R. Senthinathan, J.L. Prince, “Simultaneous Switching Ground Noise Calculation for Packaged CMOS Devices”, IEEE J. Solid-State Circuits, vol. 26, no. 11, pp. 1724–1728, November 1991.CrossRefGoogle Scholar
  20. [20]
    Simultaneous Switching Noise of CMOS Devices and Systems, R. Senthinathan, J.L. Prince, Kluwer Academic Publishers, 1994.Google Scholar
  21. [21]
    J.M. Williamson, M.S. Nakhla, Q. Zhang, P.D. van der Puije, “Ground Noise Minimization in Integrated Circuit Packages through Pin Assignment Optimization”, IEEE Trans. Components, Packaging and Manufacturing — Part B, vol. 19, no. 2, pp. 361–367, May 1996.CrossRefGoogle Scholar
  22. [22]
    M. Maleki, S. Kiaei, “Enhancement Source-Coupled Logic for Mixed-Signal VLSI Circuits”, IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 39, no. 6, pp. 399–402, June 1992.CrossRefGoogle Scholar
  23. [23]
    D.J. Allstot, S. Chee, S. Kiaei, M. Shrivastawa, “Folded Source-Coupled Logic vs. CMOS Static Logic for Low-Noise Mixed-Signal ICs”, IEEE Trans. Circuits and Systems I: Fundamental Theory and Applications, vol. 40, no. 9, pp. 553–563, September 1993.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 1999

Authors and Affiliations

  • Xavier Aragonès
    • 1
  • José Luis González
    • 1
  • Antonio Rubio
    • 1
  1. 1.Universitat Politècnica de Catalunya (UPC)Spain

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