Advertisement

Integrated circuit design (II)

A 13-bit 2.2MSample/s fourth-order cascade multi-bit Sigma-Delta modulator
  • Fernando Medeiro
  • Angel Pérez-Verdú
  • Angel Rodríguez-Vázquez
Chapter
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 480)

Abstract

Most popular ΣΔ modulator architectures incorporate a simple comparator as a quantizer [Cand92], which ensures that the re-conversion to the analog plane is perfectly linear. The drawback of such gross conversion, which on the other hand provides very robust operation, is the large quantization noise, whose effect can be attenuated only by increasing the oversampling ratio.

Keywords

Quantization Noise Effective Resolution Cascade Modulator Error Power Gain Error 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Copyright information

© Springer Science+Business Media Dordrecht 1999

Authors and Affiliations

  • Fernando Medeiro
    • 1
  • Angel Pérez-Verdú
    • 1
  • Angel Rodríguez-Vázquez
    • 1
  1. 1.Universidad de SevillaSpain

Personalised recommendations