Advertisement

Technology Impacts on Substrate Noise

  • François J. R. Clément

Abstract

The electromagnetic substrate behavior of integrated circuits (IC) is reviewed and the significant parasitic phenomenons are presented. The technology impact is examined from three complementary point of view. The respective influence of the lightly-doped and epitaxial wafers is exposed. The fabrication process steps changing the substrate characteristics are addressed for CMOS and bipolar technologies. The die-attachment is considered as a mean to reduce substrate parasitics.

Keywords

Bulk Resistivity Doping Profile Integrate Circuit Substrate Resistance Wafer Thickness 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    T. Schmerbeck, “Noise coupling in mixed-signal ASICs,” Low-power HF microelectronics: a unified approach, pp. 373-430, G. Machado — Editor, IEE, 1996.Google Scholar
  2. [2]
    N. Verghese, T. Schmerbeck, and D. Allstot, Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits, Kluwer Academic Publishers, 1995.Google Scholar
  3. [3]
    R. W. Dutton and Z. Yu, Technology CAD — Computer Simulation of IC Processes and Devices. Kluwer Academic Publishers, 1993.Google Scholar
  4. [4]
    R. M. Warner and B. L. Grung, Semiconductor-Device Electronics. Rinehart and Winston, Inc., 1991.Google Scholar
  5. [5]
    J. Y. Chen, CMOS Devices and Technology for VLSI. Prentice-Hall, 1990.Google Scholar
  6. [6]
    R. R. Troutman, Latchup on CMOS Technology — The Problem and Its Cure. Kluwer Academic Publishers, 1986.Google Scholar
  7. [7]
    T. Blalack, “Switching Noise in Mixed-Signal Integrated Circuits”, Thesis Dissertation, Stanford University Department of Electrical Engineering, December 1997.Google Scholar
  8. [8]
    A. Pun, T. Yeung, J. Lau, F. J. R. Clement and D. Su, “Experimental Results and Simulation of Substrate Noise Coupling via Planar Spiral Inductor in RF ICs”, IEEE International Electron Device Meeting, December 1997.Google Scholar
  9. [9]
    T. Blalack, J. Lau, F. Clement, and B. Wooley, “Experimental Results and Modeling of Noise Coupling in a Lightly Doped Substrate,” IEDM Technical Digest, pp. 623-626, December 1996.Google Scholar
  10. [10]
    K. Makie-Fukuda, T. Kikuchi, T. Matsuura, and M. Hotta, “Measurement of Digital Noise in Mixed-Signal Integrated Circuits,” IEEE J. Solid-State Circuits, vol. 30, no. 2, pp. 87–92, February 1995.CrossRefGoogle Scholar
  11. [11]
    T. Blalack, B. A. Wooley, “The Effects of Switching Noise on an Oversampling A/D Converter”, IEEE International Solid-State Circuit Conference, pp. 200-201, February 1995.Google Scholar
  12. [12]
    R. Merrill, W. Young, and K. Brehmer, “Effect of Substrate Material on Crosstalk in Mixed Analog/Digital Integrated Circuits,” IEEE International Electron Devices Meeting, pp. 433-436, December 1994.Google Scholar
  13. [13]
    D. Su, M. Loinaz, S. Masui, and B. Wooley, “Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits”, IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 420–430, April 1993.CrossRefGoogle Scholar
  14. [14]
    R. Gharpurey, M. C. Chang, U. Erdogan, R. Aggarwal and J. P. Mattia, “R.F. MOSFET Modeling Accounting for Distributed Substrate and Channel Resistances with Emphasis on the BSIM3v3 SPICE Model”, IEEE International Electron Device Meeting, December 1997.Google Scholar
  15. [15]
    R. Gharpurey and S. Hosur, “Transform Domain Techniques for Efficient Extraction of Substrate Parasitics”, IEEE International Conference on Computer-Aided Design, pp. 461-467, December 1997Google Scholar
  16. [16]
    J. Casalta, X. Aragones, and A. Rubio, “Substrate Coupling Evaluation in BiCMOS Technology,” IEEE J. Solid-State Circuits, vol. 32, no. 4, pp. 598–603, April 1997.CrossRefGoogle Scholar
  17. [17]
    M. Pfost, H. Rein, and T. Holzwarth, “Modeling Substrate Effects in the Design of High-Speed Si-Bipolar ICs,” IEEE J. Solid-State Circuits, vol. 31, no. 10, pp. 1493–1501, October 1996.CrossRefGoogle Scholar
  18. [18]
    K. Kwan, I. Wemple, and A. Yang, “Simulation and Analysis of Substrate Coupling in Realistically-Large Mixed-A/D Circuits,” IEEE Symposium on VLSI Circuits, pp. 184-185, June 1996.Google Scholar
  19. [19]
    R. Gharpurey and R. G. Meyer, “Modeling and Analysis of Substrate Coupling in Integrated Circuits”, IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 344–353, March 1996.CrossRefGoogle Scholar
  20. [20]
    N. K. Verghese, D. J. Allstot and M. A. Wolfe, “Verification Techniques for Substrate Coupling and Their Application to Mixed-Signal IC Design”, EEE J. Solid-State Circuits, vol. 31, no. 3, pp. 354–365, March 1996.CrossRefGoogle Scholar
  21. [21]
    A. Viviani, J. P. Raskin, D. Flandre, J. P. Colinge and D. Vanhoenacker, “Extended study of crosstalk in SOI-SIMOX substrates,” IEEE International Electron Devices Meeting, pp. 713-716, December 1995.Google Scholar
  22. [22]
    J. P. Raskin, D. Vanhoenacker, J. P. Colinge and D. Flandre, “Coupling Effects in High-Resistivity Simox Substrates for VHF and Microwaves Applications”, IEEE International SOI Conference, pp. 62-63, October 1995.Google Scholar
  23. [23]
    I. L. Temple and A. T. Yang, “Mixed-Signal Switching Noise Analysis Using Voronoi-Tesselated Substrate Macromodels”, 32nd IEEE Design Automation Conference, pp. 439-444, June 1995.Google Scholar
  24. [24]
    T. Smedes, N.P. van der Meijs, A. J. van Genderen, P.J.H. Elias and R.R.J. Vanoppen, “Layout Extraction of 3D Models for Interconnect and Substrate Parasitics”, 25th European Solid-State Device Research Conference, pp. 397-400, 1995.Google Scholar
  25. [25]
    S. Mitra, R. A. Rutenbar, L. R. Carley and D. J. Allstot, “A Methodology for Rapid Estimation of Substrate-Coupled Switching Noise”, IEEE Custom Integrated Circuit Conference, pp. 129-132, May 1995.Google Scholar
  26. [26]
    K. Joardar, “A Simple Approach to Modeling Cross-Talk in Integrated Circuits,” IEEE J. Solid-State Circuits, vol. 29, no. 10, pp. 1212–1219, October 1994.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media Dordrecht 1999

Authors and Affiliations

  • François J. R. Clément
    • 1
  1. 1.EPFLLausanneSwitzerland

Personalised recommendations