1.2 Gb/s CML Transceiver with 1M CMOS ATM/SDH Processor in a BICMOS Monochip

  • Laurent Dugoujon

Abstract

A B-ISDN Mixed Signal Design combining very high speed 1.2GHz analog PLLs with high integration level 1Mtr. CMOS Processor is depicted. Architectural choices are presented emphasizing power reduction techniques to achieve 1.5W total consumption. Low noise design style is shown with less than 18ps rms jitter performance. The practical mixed design techniques applied to this chip are described as well as DFT strategy and measurements result.

Keywords

Expense Dock 

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References

  1. [1]
    ITU-T recommendation 1-432. B-ISDN User-Network Interface Physical Layer Specifications, March 1993.Google Scholar
  2. [2]
    ITU-T Recommendation G-707(Draft). Network Node Interface for the Synchronous Digital Hierarchy (SDH), November 1995.Google Scholar
  3. [3]
    622.08 Mbps Physical Layer Specifications, ATM Forum af-phy-0046.000, January 1996.Google Scholar
  4. [4]
    A 3.3V Power Adaptive 1244/622/155 Mb/s TRANSCEIVER for ATM, SONET/SDH, Belot et al. ESSCIRC’97.Google Scholar
  5. [5]
    “SONET Transport Systems: Common Criteria”, BellCore GR-253-CORE, December 1995.Google Scholar
  6. [6]
    Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal ICs, K. Su et al. IEEE JSSC, April 1993.Google Scholar
  7. [7]
    SCA Preliminary Evaluation, Internal note ST-C.R&D, 5 June 1997.Google Scholar
  8. [8]
    Modélisation du couplage substrat, B. Salvador, ENSERG June 1997.Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 1999

Authors and Affiliations

  • Laurent Dugoujon
    • 1
  1. 1.STMicroelectronicsCrollesFrance

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