In this chapter two implementations are presented. They are a 1.5V–100 µW ∆∑ modulator [Pel 97c] which is a single ended implementation of a second order modulator. The second implementation is a 900 mV–40 µW ∆∑ modulator [Pel 98b][Pel 98a]. The latter is a fully differential implementation of a third order single loop topology.
KeywordsSupply Voltage Signal Bandwidth Resistive Divider Delay Integrator Clock Driver
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