Logic Level Modeling

  • Donald E. Thomas
  • Philip R. Moorby


To this point, we have concentrated mostly on behavioral modeling of a digital system. Behavioral models are more concerned with describing the abstract functionality of a module, regardless of its actual implementation. Logic level modeling is used to model the logical structure of a module, specifying its ports, submodules, logical function, and interconnections in a way that directly corresponds to its implementation. This chapter presents the Verilog constructs that allow us to describe the logical function and structure of a system.


Combinational Logic NAND Gate Gate Level Module Definition Delay Specification 


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Copyright information

© Springer Science+Business Media New York 1998

Authors and Affiliations

  • Donald E. Thomas
    • 1
  • Philip R. Moorby
    • 2
  1. 1.Carnegie Mellon UniversityUSA
  2. 2.Synapix, Inc.USA

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