Global Transformation Strategies for Power and Storage Size Reduction
In this chapter, the main focus will be on global transformations which improve the original code in terms of DTSE related cost factors. First, data-flow transformations will be considered in section 8.1 to section 8.3. They allow to remove redundant access in the data-flow and they serve as enablerfor the subsequent transformation steps by removing data-flow bottle-necks wherever it is cost effective to do so.
Then, global loop (and other control-flow) transformations are treated (in section 8.4 and following). We review the classical system organization and identify the problem of synchronization as the cause of the typical area and power cost inefficiencies of this organization. These inefficiencies are mainly located in the buffers between large sub-systems. Our strategy to reduce these buffers and to improve the access locality is based on loop transformations and is able to deal with stringent synchronization constraints. The strategy is applicable when multi-media applications are mapped on custom processors but also towards programmable processors or embedded processor cores. To illustrate the effectiveness and feasibility of this strategy we use a relevant class of multimedia applications as a red-thread example throughout this chapter.
KeywordsMotion Vector Buffer Size Loop Nest Input Buffer Strip Mining
Unable to display preview. Download preview PDF.