In our design methodology, the memory architecture is optimized as a first step before doing the detailed scheduling, and data-path and controller synthesis. Therefore, it has to provide sufficient storage bandwidth (parallel memory ports) such that the application can be scheduled within the cycle budget afterwards. Determining optimal constraints for the subsequent memory allocation and assignment tasks such that the cycle budget can still be met, is the task of storage-bandwidth optimization. This chapter explains what Storage Cycle Budget Distribution is about, with a main focus on the storage bandwidth optimization step. It illustrates its effect and importance on an example. It shows that it is important to take into account which data is being accessed in parallel, instead of only considering the number of simultaneous data accesses. This leads to a problem formulation in terms of the optimization of a conflict graph, for which a cost function is derived at the end of the chapter. The last sections explain how the storage-bandwidth optimization task can be implemented, especially for flat flow graphs as found mainly in network component applications. Extensions needed for hierarchical flow graphs found in RMSP applications are discussed only very briefly.
KeywordsData Access Chromatic Number Basic Group Memory Allocation Memory Hierarchy
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