Abstract
In this chapter several issues concerning system-level synthesis starting from VHDL specifications are discussed. We concentrate here on aspects which are characteristic to the synthesis of hardware components. Specifications containing subprograms and interacting processes are of main interest in this context. The last section is devoted to the problem of specifying timing constraints and of hardware synthesis under restrictions imposed by such constraints.
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© 1998 Springer Science+Business Media Dordrecht
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Eles, P., Kuchcinski, K., Peng, Z. (1998). Synthesis of Advanced Features. In: Eles, P., Kuchcinski, K., Peng, Z. (eds) System Synthesis with VHDL. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-2789-0_7
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DOI: https://doi.org/10.1007/978-1-4757-2789-0_7
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-5024-6
Online ISBN: 978-1-4757-2789-0
eBook Packages: Springer Book Archive