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Prototyping and Emulation

  • Wolfgang Rosenstiel
Chapter

Abstract

ASICs will continue to grow increasingly complex. Errors of specification, design and implementation are unavoidable. Consequently, designers need validation methods and tools to ensure a perfect design before the production is started. Errors caught after fabrication incur not only added production costs, but also delay the product, which is an increasingly serious detriment in today’s fast-paced international markets. “First-time-right silicon” is, therefore, one of the most important goals of chip-design projects.

Keywords

Formal Verification Fault Simulation Emulation System Logic Simulation VHDL Code 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media Dordrecht 1997

Authors and Affiliations

  • Wolfgang Rosenstiel
    • 1
  1. 1.Technische InformatikUniversität TübingenTübingenGermany

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