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A Model for Exploring Hardware/Software Trade-offs and Evaluating Design Alternatives

  • Sanjaya Kumar
  • James H. Aylor
  • Barry W. Johnson
  • Wm. A. Wulf
  • Ronald D. Williams
Part of the Current Issues in Electronic Modeling book series (CIEM, volume 8)

Abstract

To address the separation between the hardware and software domains, this chapter presents an abstract hardware/software model employing a unified representation that supports the early exploration of hardware/software trade-offs and the evaluation of design alternatives with respect to multiple metrics. Using this model, systems can be evaluated at different levels of detail, allowing those aspects of interest to be focused on. This model has been implemented in the Advanced Design Environment Prototyping Tool (ADEPT). The abstract hardware/software model is demonstrated on two examples: a “best-fit ellipse “feature extraction algorithm and a stylus tracking system.

Keywords

Fast Fourier Transform Control Flow Graph Feature Extraction Algorithm Data Flow Graph General Purpose Processor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    Franke, D. W., M. K. Purvis, “Hardware/Software Codesign: A Perspective,” Proceedings of the 13th International Conference on Software Engineering, May 13–16, 1991, pp. 344–352.CrossRefGoogle Scholar
  2. [2]
    Peng, Z., J. Fagerström, K. Kuchcinski, “A Unified Approach to Evaluation and Design of Hardware/Software Systems,” 1991 Workshop on Hardware/Software Codesign, Technical Report No. MCC-CAD-156–91.Google Scholar
  3. [3]
    Roman, G., et al., “A Total System Design Framework,” IEEE Computer, May 1984, pp. 15–26.Google Scholar
  4. [4]
    Smith, C. U., L. G. Williams, “Software Performance Engineering: A Case Study including Performance Comparison with Design Alternatives,” IEEE Transactions on Software Engineering, Vol. 19, July 1993, pp. 720–741.CrossRefGoogle Scholar
  5. [5]
    Kumar, S., J. H. Aylor, B. W. Johnson, W. A. Wulf, The Codesign of Embedded Systems: A Unified Hardware/Software Representation, Kluwer Academic Publishers, Boston, Massachusetts, 1996.CrossRefGoogle Scholar
  6. [6]
    De Micheli, G., “Extending CAD Tools and Techniques,” IEEE Computer, January 1993, pp. 84–87.Google Scholar
  7. [7]
    Proceedings 4th International Workshop on Hardware/Software Co-Design CODES/CASHE ‘96, Pittsburgh, Pennsylvania, March 18–20, 1996, USA.Google Scholar
  8. [8]
    Fuhrman, T., et al., Industry Panel on Hardware/Software Codesign, 4th International Workshop on Hardware/Software Co-Design, Pittsburgh, Pennsylvania, March 18–20, 1996, USA.Google Scholar
  9. [9]
    Kumar, S., R. H. Klenke, J. H. Aylor, B. W. Johnson, R. D. Williams, R. Waxman, “ADEPT: A Unified System Level Modeling Design Environment,” Proceedings of the 1st Annual RASSP Conference, Arlington, Virginia, August 15–18, 1994, pp. 114–123.Google Scholar
  10. [10]
    Myers, G. J., Advances in Computer Architecture, John Wiley and Sons, New York, 1982.MATHGoogle Scholar
  11. [11]
    Kumar, S., J. H. Aylor, B. W. Johnson, W. A. Wulf, R. D. Williams, “Early Performance Evaluation using Abstract Hardware/Software Models,” VHDL International User’s Forum Spring 1996 Conference (VIUF ‘96), February 28 — March 2, 1996, Santa Clara, California, pp. 51–60.Google Scholar
  12. [12]
    Linger, R. C., H. D. Mills, B. I. Witt, Structured Programming Theory and Practice, Addison-Wesley Publishing, Reading, Massachusetts, 1979.MATHGoogle Scholar
  13. [13]
    Aho, A. V., R. Sethi, J. D. Ullman, Compilers Principles, Techniques, and Tools, Addison-Wesley Publishing Company, Reading, Massachusetts, 1986.Google Scholar
  14. [14]
    Sholl, H. A., T. L. Booth, “Software Performance Modeling using Computation Structures,” IEEE Transactions on Software Engineering, Vol. SE-1, No. 4, December 1975, pp. 414–420.CrossRefGoogle Scholar
  15. [15]
    Kumar, S., J. H. Aylor, B. W. Johnson, W. A. Wulf, “A Framework for Hardware/Software Codesign,” IEEE Computer, December 1993, pp. 39–45.Google Scholar
  16. [16]
    Miller, W. H., B. W. Johnson, “Automatic Classification of Aluminum Defects,” Department of Electrical Engineering, University of Virginia, Technical Report No. UVA/5–38459/EE94, October 31, 1994.Google Scholar
  17. [17]
    Schaefer, P., R. D. Williams, “The Stylus Tracking Project,” Department of Electrical Engineering, University of Virginia, Technical Report, 1995.Google Scholar
  18. [18]
    Owen, R. E., “A 15 Nanosecond Complex Multiplier-Accumulator for FFTs,” ICASSP ‘87, 1987, pp. 527–530.Google Scholar
  19. [19]
    Smith, C. U., R. R. Gross, “Technology Transfer between VLSI Design and Software Engineering: CAD Tools and Design Methodologies,” Proceedings of the IEEE, Vol. 74, No. 6, June 1986, pp. 875–885.CrossRefGoogle Scholar
  20. [20]
    Franke, D. W., M. K. Purvis, “An Overview of Hardware/Software Codesign,” International Symposium on Circuits & Systems, May 1992, pp. 2665–2668.Google Scholar
  21. [21]
    Estrin, G., R. S. Fenchel, R. R. Razouk, M. K. Vernon, “SARA: Modeling, Analysis, and Simulation Support for Design of Concurrent Systems,” IEEE Transactions on Software Engineering, Vol. SE-12, No. 2, February 1986, p. 293–311.CrossRefGoogle Scholar
  22. [22]
    Scientific Engineering Software, Inc. SES/Workbench User ‘s Guide, Austin, Texas, April 1989.Google Scholar
  23. [23]
    Frank, G. A., et al. “An Architecture Design and Assessment System for Software/Hardware Codesign”, Proceedings 22nd Design Automation Conference, 1985, pp. 417–424.Google Scholar
  24. [24]
    Srivastava, M. B., R. W. Broderson. “Rapid-Prototyping of Hardware and Software in a Unified Framework”, Proceedings of the International Conference on Computer-Aided Design, 1991, pp. 152–155.Google Scholar
  25. [25]
    Kalavade, A., E. A. Lee, “A Hardware-Software Codesign Methodology for DSP Applications,” IEEE Design and Test, September 1993, pp. 16–28.Google Scholar
  26. [26]
    Rose, F., T. Carpenter, S. Kumar, J. Shackleton, and T. Steeves, “A Model for the Coanalysis of Hardware and Software Architectures,” Proceedings 4th International Workshop on Hardware/Software Co-Design, Pittsburgh, Pennsylvania, March 18–20, 1996, USA, pp. 94–103.Google Scholar
  27. [27]
    Gupta, R. K., G. De Micheli, “Hardware-Software Cosynthesis for Digital Systems,” IEEE Design and Test, September 1993, pp. 29–40.Google Scholar
  28. [28]
    Ernst, R., J. Henkel, T. Benner, “Hardware-Software Cosynthesis for Microcontrollers,” IEEE Design and Test, December 1993, pp. 64–75.Google Scholar
  29. [29]
    Barros, E., W. Rosenstiel, “A Method for Hardware/Software Partitioning,” Proceedings Compeuro, IEEE CS Press, 1992.Google Scholar
  30. [30]
    Kalavade, A., E. Lee, “A Global Criticality/Local Phase Driven Algorithm for the Constrained Hardware/Software Partitioning Problem,” 3rd International Workshop on Hardware/Software Codesign, Grenoble, France, September 22–24, 1994, pp. 42–48.Google Scholar
  31. [31]
    Balboni, A., W. Fornaciari, and D. Sciuto, “Partitioning and Exploration Strategies in the TOSCA Co-Design Flow,” Proceedings 4th International Workshop on Hardware/Software Co-Design, Pittsburgh, Pennsylvania, March 18–20, 1996, USA, pp. 62–69.Google Scholar
  32. [32]
    Knudsen, P., J. Madsen, “PACE: A Dynamic Programming Algorithm for Hardware/Software Partitioning,” Proceedings 4th International Workshop on Hardware/Software Co-Design, Pittsburgh, Pennsylvania, March 18–20, 1996, USA, pp. 85–92.Google Scholar
  33. [33]
    Gupta, R., “A Framework for Interactive Analysis of Timing Constraints in Embedded Systems,” Proceedings 4th International Workshop on Hardware/Software Co-Design, Pittsburgh, Pennsylvania, March 18–20, 1996, USA, pp. 44–51.Google Scholar
  34. [34]
    Ye, W., R. Ernst, T. Benner, and J. Henkel, “Fast Timing Analysis for Hardware-Software Co-Synthesis,” Proceedings IEEE International Conference on Computer Design, 1993.Google Scholar
  35. [35]
    Li, S., S. Malik, “Performance Analysis of Embedded Software using Implicit Path Enumeration,” Proceedings 32nd Design Automation Conference, San Francisco, California, June 12–16, 1995, pp. 456–461.Google Scholar
  36. [36]
    Yen, T., W. Wolf, “Performance Estimation for Real-Time Distributed Embedded Systems,” International Conference on Computer Design: VLSI in Computers and Processors, Austin, Texas, October 2–4, 1995, pp. 64–69.Google Scholar
  37. [37]
    Aylor, J. H., R. Waxman, B. W. Johnson, R. D. Williams, “The Integration of Performance and Functional Modeling in VHDL” in Performance and Fault Modeling with VHDL, J. Schoen, ed., Prentice-Hall, Englewood Cliffs, N.J., 1992.Google Scholar
  38. [38]
    Meyassed, M., R. McGraw, J. Aylor, R. Klenke, R. Williams, F. Rose, and J. Shackleton, “A Framework for the Development of Hybrid Models,” Proceedings 2nd Annual RASSP Conference, pp 147–154, Arlington, VA, July, 1995.Google Scholar
  39. [39]
    Kumar, S., F. Rose, “Integrated Simulation of Performance Models and Behavioral Models,” VHDL International User’s Forum Fall 1996 Conference (VIUF ‘96), October 27–30, 1996, Durham, North Carolina.Google Scholar
  40. [40]
    Ammar, R. A., B. Qin, “An Approach to Derive Time Costs for Sequential Computations,” Journal Systems Software, Vol. 11, 1990, pp. 173–180.CrossRefGoogle Scholar
  41. [41]
    Chu, W. W., L. J. Holloway, M. Lan, K. Efe, “Task Allocation in Distributed Data Processing,” IEEE Computer, November 1980, pp. 57–69.Google Scholar
  42. [42]
    Peterson, J. L., Petri Net Theory and the Modeling of Systems, Englewood Cliffs, N.J., Prentice-Hall, 1981.Google Scholar
  43. [43]
    Kavi, K. M., B. P. Buckles, U. N. Bhat, “Isomorphisms between Petri nets and Dataflow Graphs,” IEEE Transactions on Software Engineering, Vol. SE-13, No. 10, October 1987, pp. 1127–1133.CrossRefGoogle Scholar
  44. [44]
    Auletta, R. J., An Uninterpreted Model for Hardware Description Languages, Department of Electrical Engineering, Ph. D. Dissertation, University of Virginia, May 1987.Google Scholar
  45. [45]
    Calvez, J. P., D. Heller, and O. Pasquier, “Uninterpreted Co-Simulation for Performance Evaluation,” Proceedings 4th International Workshop on Hardware/Software Co-Design, Pittsburgh, Pennsylvania, March 18–20, 1996, USA, pp. 132–139.Google Scholar
  46. [46]
    Hoffman, R., “A Classification of Interpreter Systems,” Microprocessing and Microprogramming, 12, 1983, pp. 3–8.CrossRefGoogle Scholar
  47. [47]
    Frank, G. A., D. L. Franke, W. F. Ingogly, “An Architecture Design and Assessment System,” VLSI Design, August 1985, pp. 30–50.Google Scholar
  48. [48]
    Smith, C. U., “Robust Models for the Performance Evaluation of Software/Hardware Design,” International Workshop on Timed Petri Nets, Torino, Italy, July 1–3, 1985, pp. 172–180.Google Scholar
  49. [49]
    Miller, R. E., “A Comparison of Some Theoretical Models of Parallel Computation,” IEEE Transactions on Computer, Vol. C-22, No. 8, August 1973, pp. 710–717.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media Dordrecht 1997

Authors and Affiliations

  • Sanjaya Kumar
    • 1
  • James H. Aylor
    • 2
  • Barry W. Johnson
    • 2
  • Wm. A. Wulf
    • 3
  • Ronald D. Williams
    • 2
  1. 1.Honeywell Technology CenterUSA
  2. 2.Department of Electrical EngineeringUniversity of VirginiaUSA
  3. 3.Department of Computer ScienceUniversity of VirginiaUSA

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