Skip to main content
SpringerLink
Log in
Book cover

Analog Circuit Design pp 105–120Cite as

Linearizing a 128 Msample/S ADC

  • Chapter

Abstract

We describe a 128 Msample/s 12-bit analog-to-digital converter IC that has special circuitry on-chip to reduce the nonlinearities that make most ADCs unsuitable for highdynamic-range spectrum analysis and digital receiver applications. Dither, dynamic element matching, and output data scrambling combine to achieve 0.05-LSB DNL.

This is a preview of subscription content, log in via an institution.

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD   169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Bartz, M., et al., “Dither error correction”, U.S. Patent 5189418, Feb., 1993.

    Google Scholar 

  2. Hilton, H, “A 10MHz Analog-to-Digital Converter with 110-dB Linearity,” Hewlett-Packard Journal, pp. 105–112, Oct. 1993.

    Google Scholar 

  3. Fattaruso, et al., “Self-Calibration Techniques for a Second-Order Multibit Sigma-Delta Modulator,” IS S CC Digest Of Technical Papers,” pp. 228–229, Feb. 1993

    Google Scholar 

  4. Patent applied for.

    Google Scholar 

  5. Van Valberg, J., et al., “An 8b 650MHz Folding ADC”, ISSCC Digest Of Technical Papers pp. 34–35; Feb., 1992.

    Google Scholar 

  6. Jewett, R., et al., “A 12b 128Msample/s ADC with 0.05LSB DNL”, ISSCC Digest Of Technical Papers, pp. 138–139; Feb., 1997.

    Google Scholar 

  7. Veendrick, H.J.M., “The Behavior Of Flip-Flops Used As Synchronizers And Prediction Of Their Failure Rate,” IEEE J. Solid-State Circuits, SC-15, pp. 169–176, Apr. 1980.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. High Speed Electronics Department, Hewlett-Packard Labs, Palo Alto, CA, USA

    Robert Jewett, Ken Poulton, Kuo-Chiang Hsieh & Joey Doernberg

Authors
  1. Robert Jewett
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Ken Poulton
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Kuo-Chiang Hsieh
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Joey Doernberg
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Philips Research Laboratories, Eindhoven, The Netherlands

    Rudy J. van de Plassche

  2. T.U. Delft, The Netherlands

    Hohan H. Huijsing

  3. K.U. Leuven, Heverlee, Belgium

    Willy Sansen

Rights and permissions

Reprints and permissions

Copyright information

© 1997 Springer Science+Business Media Dordrecht

About this chapter

Cite this chapter

Jewett, R., Poulton, K., Hsieh, KC., Doernberg, J. (1997). Linearizing a 128 Msample/S ADC. In: van de Plassche, R.J., Huijsing, H.H., Sansen, W. (eds) Analog Circuit Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-2602-2_6

Download citation

  • DOI: https://doi.org/10.1007/978-1-4757-2602-2_6

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-5185-4

  • Online ISBN: 978-1-4757-2602-2

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation