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Linearizing a 128 Msample/S ADC

  • Robert Jewett
  • Ken Poulton
  • Kuo-Chiang Hsieh
  • Joey Doernberg

Abstract

We describe a 128 Msample/s 12-bit analog-to-digital converter IC that has special circuitry on-chip to reduce the nonlinearities that make most ADCs unsuitable for highdynamic-range spectrum analysis and digital receiver applications. Dither, dynamic element matching, and output data scrambling combine to achieve 0.05-LSB DNL.

Keywords

Probability Density Function Linear Feedback Shift Register Transfer Curve Dynamic Element Match Dither Signal 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

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    Bartz, M., et al., “Dither error correction”, U.S. Patent 5189418, Feb., 1993.Google Scholar
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    Hilton, H, “A 10MHz Analog-to-Digital Converter with 110-dB Linearity,” Hewlett-Packard Journal, pp. 105–112, Oct. 1993.Google Scholar
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    Fattaruso, et al., “Self-Calibration Techniques for a Second-Order Multibit Sigma-Delta Modulator,” IS S CC Digest Of Technical Papers,” pp. 228–229, Feb. 1993Google Scholar
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    Patent applied for.Google Scholar
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    Van Valberg, J., et al., “An 8b 650MHz Folding ADC”, ISSCC Digest Of Technical Papers pp. 34–35; Feb., 1992.Google Scholar
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    Jewett, R., et al., “A 12b 128Msample/s ADC with 0.05LSB DNL”, ISSCC Digest Of Technical Papers, pp. 138–139; Feb., 1997.Google Scholar
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Copyright information

© Springer Science+Business Media Dordrecht 1997

Authors and Affiliations

  • Robert Jewett
    • 1
  • Ken Poulton
    • 1
  • Kuo-Chiang Hsieh
    • 1
  • Joey Doernberg
    • 1
  1. 1.High Speed Electronics DepartmentHewlett-Packard LabsPalo AltoUSA

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