Advertisement

Architectures and Circuits for A/D and D/A Conversion in CMOS Integrated Systems for Telecom Applications

  • Jan Sevenhans
  • Zhong-Yuan Chang

Abstract

Emerging telecom systems such as ADSL, VDSL demand state—of—the—art high speed and high resolution A/D and D/A converters. Moreover, cost and power consumption issues require the use of specific A/D and D/A architectures to achieve the wanted resolution at the required speed for the minimum power. In the first part of this paper an overview is given of various A/D and D/A converter architectures used in Alcatel telecom systems over the past 15 years. Emphasis is placed on the evolution of A/D and D/A converters for today’s ADSL applications. Then design considerations for high speed and high resolution pipelined A/D converters for future VDSL technology will be addressed.

Keywords

Gain Error Telecom Application Capacitor Mismatch Folding Signal Stop Band Attenuation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    Z.Y. Chang et al, “A CMOS analog Front End circuit for an FDM—based ADSL system” proceedings IEEE ISSCC’96 Google Scholar
  2. [2]
    J. Sevenhans et al, “A Versatile digital signal processor in 1.2μ cmos with on chip d/a and a/d conversion serving 4 speech channels in a new generation subscriber line circuit” proceedings ESSCIRC’90Google Scholar
  3. [3]
    D. Sallaerts et al, “A 160 kbit/s Transceiver for Digital subscriber loop” proceedings IEEE lSSCC’86 Google Scholar
  4. [4]
    Thomas Hack , “IQ Sampling Yields Flexible Demodulators” RF Design, April 1991 pp40–50Google Scholar
  5. [5]
    Hans.J. Dressler, “Interpolative bandpass A/D conversion” Elsevier, Signal Processing 22 1991Google Scholar
  6. [6]
    J. Vanneuville et al, “A transistor only sigma—delta a/d convertor for a cmos speech codec” proceedings ESSCIRC’90Google Scholar
  7. [7]
    Y.L. Cheung et al, “A Sampled—Data Switched—Current Analog 16—Tap FIR Filter with Digitalally Programmable Coefficients in 0.8µm CMOS” proceedings IEEE ISSCC’96 SA19.2 pp314–315Google Scholar
  8. [8]
    T.B. Cho and P.Gray, “A 10—b 20Msamples/s 35mW pipeline A/D converter,” IEEE J. Sol id—State Circuits, Vol.30, NO.3, pp 166–172, March 1995CrossRefGoogle Scholar
  9. [9]
    D.W. Cline and P. Gray, “A Power optimized 13—b 5Msamples/s analog to digital converter in 1.2um CMOS,” IEEE J. Solid—State Circuits, Vol.31, NO.3, pp294–303, March 1996CrossRefGoogle Scholar
  10. [10]
    W-H Song et al, “A 10—b 20—Msamples/s low power CMOS ADC,” IEEE J. Solid—State Circuits, Vol.30, NO.5, pp514–521, May 1995CrossRefGoogle Scholar
  11. [11]
    K. Nakamura et al, “A 85mW, 10b, 40Msamples/s CMOS parallel—pipelined ADC,” IEEE.J. Solid—State Circuits, Vol.30, NO.3, pp173–183, March 1995CrossRefGoogle Scholar
  12. [12]
    M. K. Mayes and S.W.Chin, “Monolithic low—power 16b 1 Msamples/s self—calibrating pipeline ADC,” proceedings IEEE ISSCC’96 SA 19.1 pp312–313Google Scholar
  13. [13]
    P.C. Yu and H.S.Lee, “A 2.5 V 12b 5Ms/s pipelined CMOS ADC,” proceedings IEEE ISSCC’96 SA19.2 pp314–315Google Scholar
  14. [14]
    S.I. Lim et al, “A 12b 10Mhz 250mW CMOS AD converter,” proceedings IEEE ISSCC’96 SA 19. 2 pp316–317Google Scholar
  15. [15]
    K. Y. Kim et al, “A 10b 100Ms/s CMOS AD converter,” proceedings IEEE CICC’96 SA20. 3 pp419–422Google Scholar
  16. [16]
    [18]. K. Nagaraj et al, “A 8—bit 50 Ms/s pipelined A/D converter with an area and power efficient architecture,” proceedings IEEE CICC’96 SA20.3 pp423–426Google Scholar
  17. [17]
    J. Yang and H.S. Lee, “A CMOS 12—b 4Mhz pipelined A/D converter with commutative feedback capacitor,” proceedings IEEE CICC’96 SA20.3 pp427–430Google Scholar
  18. [18]
    Y.M Lin, B. Kim and P. Graly, “A 13—b 2.5 Mhz self—calibrated pipelined A/D converters in 3um CMOS,” IEEE J. Solid—State Circuits, Vol.26, NO.4, pp628–635, April 1991CrossRefGoogle Scholar
  19. [19]
    [ADI] Analog Devices, “12—bit, 41 Msps Monolithic A/D converterGoogle Scholar
  20. [20]
    [BBI] Burr Brown, “12—bit, 40Mha sampling Analog—to—Digital converter”Google Scholar
  21. [21]
    L. Singer and T. Brooks, “A 14—bit 10Mhz calibration—free CMOS pipelines ADC,” IEEE V LSI’ 96 pp94–95, 1996Google Scholar
  22. [22]
    B. Nauta and A. G. W. Venes, “A 70—Ms/s 110—mW 8—b CMOS folding and interpolating A/D converter,” IEEE J. Solid—State Circuits, Vol 30, NO.12, pp 1302–1307, Dec. 1995CrossRefGoogle Scholar
  23. [23]
    A. Venes and R. Van de Plassche, “An 80Mhz 80mW 8b folding A/D converter with distributed T/H preprocessing,” IEEE ISSCC’96 pp318–319, 1996Google Scholar
  24. [24]
    R. Jewett et al, “A 12b 128Msamples/s ADC with 0.05LSB DNL” proceedings IEEE ISSCC’97 pp138–139Google Scholar
  25. [25]
    S-U Kwak et al, “A 15b 5Msamples/s low—spurious CMOS ADC” proceedings IEEE ISSCC’96 pp146–147Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 1997

Authors and Affiliations

  • Jan Sevenhans
    • 1
  • Zhong-Yuan Chang
    • 1
  1. 1.Alcatel BellAntwerpBelgium

Personalised recommendations