Synthesizer Architectures

  • Cicero Vaucher


Synthesizer architectures suitable for high integration level are reviewed and qualitatively analysed w.r.t. complexity, power dissipation, phase noise and spurious performance. The effect of the PLL noise sources on the output noise is described, and the noise performance of a double loop configuration is presented.


Phase Noise Power Dissipation Phase Detector Charge Pump Loop Filter 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media Dordrecht 1997

Authors and Affiliations

  • Cicero Vaucher
    • 1
  1. 1.Philips Research LaboratoriesEindhovenThe Netherlands

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